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公开(公告)号：KR100794658B1
公开(公告)日：2008-01-14
申请号：KR1020060063936
申请日：2006-07-07
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L21/76898 , H01L23/3128 , H01L23/3178 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/82 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02313 , H01L2224/02372 , H01L2224/02379 , H01L2224/0239 , H01L2224/036 , H01L2224/0401 , H01L2224/04105 , H01L2224/05009 , H01L2224/05548 , H01L2224/06181 , H01L2224/11334 , H01L2224/11462 , H01L2224/12105 , H01L2224/13024 , H01L2224/13025 , H01L2224/16145 , H01L2224/16235 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06586 , H01L2225/1058 , H01L2924/00 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/01028 , H01L2224/03
Abstract: Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate.
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公开(公告)号：KR1020080004958A
公开(公告)日：2008-01-10
申请号：KR1020060063936
申请日：2006-07-07
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L21/76898 , H01L23/3128 , H01L23/3178 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/82 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02313 , H01L2224/02372 , H01L2224/02379 , H01L2224/0239 , H01L2224/036 , H01L2224/0401 , H01L2224/04105 , H01L2224/05009 , H01L2224/05548 , H01L2224/06181 , H01L2224/11334 , H01L2224/11462 , H01L2224/12105 , H01L2224/13024 , H01L2224/13025 , H01L2224/16145 , H01L2224/16235 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06586 , H01L2225/1058 , H01L2924/00 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/01028 , H01L2224/03
Abstract: A semiconductor chip, a manufacturing method thereof, and a chip stack package are provided to completely suppress a leakage current by arbitrarily adjusting a spacing between the semiconductor chip and a semiconductor substrate. A semiconductor chip includes a bonding pad(5), an electric line(7), a semiconductor support(9), and a protective film(3). The bonding pad is located on a semiconductor substrate. The electric line is contacted with the bonding pad and elongated to outside from a semiconductor substrate edge. The semiconductor support is contacted with the electric line and spaced apart from the semiconductor substrate. The protective film is arranged between the electric line and the semiconductor substrate. A conductive pattern covers a sidewall or a bottom of the semiconductor support and is contacted with the electric line.
Abstract translation: 提供半导体芯片及其制造方法以及芯片堆叠封装，以通过任意调整半导体芯片和半导体基板之间的间隔来完全抑制漏电流。 半导体芯片包括焊盘（5），电线（7），半导体支撑（9）和保护膜（3）。 接合焊盘位于半导体衬底上。 电线与焊盘接触并从半导体衬底边缘延伸到外部。 半导体支撑件与电线接触并与半导体衬底间隔开。 保护膜配置在电线与半导体基板之间。 导电图案覆盖半导体支撑件的侧壁或底部并与电线接触。
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公开(公告)号：KR1020070112646A
公开(公告)日：2007-11-27
申请号：KR1020060045802
申请日：2006-05-22
Applicant: 삼성전자주식회사
IPC: H01L23/12
CPC classification number: H01L25/50 , H01L21/76898 , H01L25/0657 , H01L29/0657 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/0557 , H01L2224/06181 , H01L2224/13025 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2225/06586 , H01L2924/0002 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01093 , H01L2224/11 , H01L2224/05552
Abstract: A wafer package and a manufacturing method thereof are provided to minimize reliability reduction of connectivity due to an excessive protrusion of a connection device by forming the connection device penetrating a floor of a trench, after forming the trench according to a scribe line. A plurality of semiconductor chips having a connection pad are formed on a wafer(S10). A trench is formed under the connection pad by patterning a bottom surface of the wafer(S30). A via hole exposing the bottom surface of the connection pad is formed by patterning the bottom surface of the trench(S50). A connection device is formed and connected to the connection pad through the via hole(S60).
Abstract translation: 提供晶片封装及其制造方法，以便在根据划线形成沟槽之后，通过形成贯穿沟槽的底板的连接装置，由于连接装置的过度突出而最小化连接性的可靠性。 在晶片上形成具有连接焊盘的多个半导体芯片（S10）。 通过图案化晶片的底面，在连接焊盘下形成沟槽（S30）。 通过图案化沟槽的底面形成露出连接焊盘的底面的通孔（S50）。 连接装置形成并通过通孔与连接垫连接（S60）。
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公开(公告)号：KR1020070073184A
公开(公告)日：2007-07-10
申请号：KR1020060000786
申请日：2006-01-04
Applicant: 삼성전자주식회사
CPC classification number: H01L25/0657 , H01L21/76898 , H01L23/481 , H01L25/50 , H01L2224/02371 , H01L2224/02372 , H01L2224/0401 , H01L2224/13025 , H01L2224/274 , H01L2225/06513 , H01L2225/06541 , H01L2924/01079 , H01L2924/01087
Abstract: A wafer level package and a method for manufacturing the same are provided to simplify a manufacturing process by improving a structure of a part connected electrically with an external substrate. A semiconductor chip(10) includes an upper face and a side face connected to the upper surface. A plurality of pads(5) are formed on the upper face. A conductive body(30) includes a first pattern part and a second pattern part. The first pattern part is electrically connected to each pad. The second pattern part is electrically connected to the first pattern part and is isolated from the side face. A protective pattern(20) is formed on the upper face and includes an opening for exposing the pads.
Abstract translation: 提供晶片级封装及其制造方法，以通过改善与外部基板电连接的部件的结构来简化制造工艺。 半导体芯片（10）包括上表面和连接到上表面的侧面。 在上表面上形成有多个焊盘（5）。 导电体（30）包括第一图案部分和第二图案部分。 第一图案部分电连接到每个垫。 第二图案部分电连接到第一图案部分并且与侧面隔离。 保护图案（20）形成在上表面上，并且包括用于露出垫的开口。
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公开(公告)号：KR100639703B1
公开(公告)日：2006-10-30
申请号：KR1020050072883
申请日：2005-08-09
Applicant: 삼성전자주식회사
Abstract: A method for compensating for an undercut of a metal base layer is provided to guarantee the area of a metal base layer by compensating for an undercut of a metal base layer under a redistribution layer or a solder bump. An insulation layer is formed on a semiconductor wafer(91). The insulation layer is covered with a multilayered metal base layer(92). A photomask having an open part is formed on the metal base layer(93). The photomask is dry-etched to form a concave part that rounds toward the inner lower part of the inner wall of the open part adjacent to the metal base layer(94). The open part including the concave part is filled with a plating layer(95). The photomask is eliminated(96). The metal base layer outside the plating layer is wet-etched(97). The metal base layer that is etched toward the inside of the outer surface of the plating layer on the upper part of a protrusion part is reduced by the protrusion part of the plating layer filled in the concave part so that an area of the metal base layer under the plating layer is guaranteed. The plating layer can be a redistribution layer or a solder plating layer for a solder bump.
Abstract translation: 提供一种用于补偿金属基层的底切的方法，以通过补偿重新分布层或焊料凸块下方的金属基层的底切来保证金属基层的面积。 在半导体晶片（91）上形成绝缘层。 绝缘层覆盖有多层金属基层（92）。 在金属基底层（93）上形成具有开口部分的光掩模。 对光掩模进行干蚀刻，形成朝向与金属基底层（94）邻接的开口部的内壁的内侧下部呈圆形的凹部。 包括凹部的开口部分填充有镀层（95）。 光罩被消除（96）。 对电镀层外部的金属基层进行湿蚀刻（97）。 通过填充在凹部中的镀层的突出部分来减少在突出部分的上部上朝向镀层的外表面内侧蚀刻的金属基底层，从而使金属基底层的面积 在镀层下有保证。 镀层可以是用于焊料凸块的再分布层或焊料镀层。
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Patent Agency Ranking
公开(公告)号：KR1020060016217A
公开(公告)日：2006-02-22
申请号：KR1020040064586
申请日：2004-08-17
Applicant: 삼성전자주식회사
IPC: H01L23/50 , H01L23/28 , H01L23/12 , H01L23/485
CPC classification number: H05K3/3436 , H01L21/563 , H01L23/3114 , H01L23/3128 , H01L23/3171 , H01L23/525 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/05655 , H01L2224/10126 , H01L2224/11334 , H01L2224/13022 , H01L2224/13099 , H01L2224/16 , H01L2224/73253 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/12044 , H01L2924/14 , H01L2924/15311 , H01L2924/16195 , H05K3/0023 , H05K2201/10977 , Y02P70/613 , Y10T29/49149 , H01L2224/05552 , H01L2924/00014 , H01L2924/013
Abstract: 솔더볼 접착 신뢰도를 높이는 반도체 패키지 및 그 제조방법에 관해 개시한다. 이를 위해 본 발명은 솔더볼이 부착된 반도체 소자 위에 절연막 대신에 고분자 감광막을 코팅하고 솔더볼 위에 있는 고분자 감광막 일부를 노광공정으로 제거하여 일정한 크기의 콘택영역을 형성한다. 따라서 고분자 감광막이 솔더볼의 접착 신뢰도를 높일 수 있다.
솔더볼 접착 신뢰도(SJR), WLCSP, 고분자 감광막.-
公开(公告)号：KR1020060011342A
公开(公告)日：2006-02-03
申请号：KR1020040060145
申请日：2004-07-30
Applicant: 삼성전자주식회사
IPC: H01L21/82
Abstract: 반도체 메모리 장치 및 그 제조 방법이 개시된다. 본 발명에 따른 반도체 메모리 장치는 반도체 칩, 반도체 칩의 입출력 패드를 개방하는 패시베이션층, 패시베이션층 상의 버퍼층, 및 패시베이션층과 버퍼층을 관통하여 퓨즈 박스를 개방하는 퓨즈 박스 홀을 매립하고 반도체 칩 가장자리 상의 버퍼층을 덮고 있는 퓨즈 커버층을 포함한다.
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公开(公告)号：KR1020060010099A
公开(公告)日：2006-02-02
申请号：KR1020040058689
申请日：2004-07-27
Applicant: 삼성전자주식회사
CPC classification number: H01L23/481 , H01L21/78 , H01L23/3128 , H01L23/525 , H01L24/02 , H01L24/10 , H01L24/13 , H01L25/0657 , H01L2224/0401 , H01L2224/13 , H01L2224/13099 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/15311 , H01L2924/30107 , H01L2924/00
Abstract: 본 발명은 웨이퍼 레벨 적층 패키지용 칩 스케일 패키지 제조 방법에 관한 것으로, 관통 전극을 형성하기 위한 레이저 드릴링 공정과 감광막을 이용한 절연층 패터닝 공정과 같은 크리티클 공정 없이 일반적인 반도체 제조 공정을 이용하여 관통 전극을 형성하기 위해서, 반도체 웨이퍼의 칩 절단 영역을 따라서 소정의 깊이로 쏘잉하여 슬롯을 형성하고, 슬롯에 층간 절연 소재의 절연층을 형성한 후 일반적인 반도체 제조 공정을 이용하여 관통 전극을 형성하는 웨이퍼 레벨 적층 패키지용 칩 스케일 패키지 제조 방법을 제공한다.
웨이퍼 레벨, 적층, 칩 스케일 패키지, 슬롯, 층간 절연층, 감광막-
公开(公告)号：KR1020040062340A
公开(公告)日：2004-07-07
申请号：KR1020030000149
申请日：2003-01-02
Applicant: 삼성전자주식회사
Inventor： 정현수
IPC: H05H1/34
Abstract: PURPOSE: A gas line connector of a plasma flood gun is provided to improve the working by using an O-ring as an air tight maintenance member. CONSTITUTION: An interconnection pipe(110) is coupled to a side wall of a processing room(101). A fixing member(130) is fixed to an outside of the interconnection pipe(110). A screw unit(131) is provided on an outside of the fixing member(130). A nut member(150) is connected to the screw unit(131) of the fixing member(130) and to a gas line. An O-ring(170) is inserted into a contactor of the nut member(150) and the interconnection pipe(110) to prevent a gas leakage. A flange unit(111a) provided with a connecting hole(111a') is formed on the interconnection pipe(110). The interconnection pipe(110) is connected to a side of an external wall of the processing room(101) by a connecting screw(180). A gas through-hole(112) is formed within the interconnection pipe(110) to be connected to a passing through-hole(101a).
Abstract translation: 目的：提供等离子喷枪的气体线连接器，通过使用O形圈作为气密维护构件来改善工作。 构成：互连管（110）联接到处理室（101）的侧壁。 固定构件（130）固定在互连管（110）的外侧。 螺钉单元（131）设置在固定构件（130）的外侧。 螺母构件（150）连接到固定构件（130）的螺钉单元（131）和气体管线。 O形圈（170）插入到螺母构件（150）和互连管（110）的接触器中，以防止气体泄漏。 在互连管（110）上形成设有连接孔（111a'）的凸缘单元（111a）。 互连管（110）通过连接螺钉（180）连接到加工室（101）的外壁的一侧。 在所述互连管（110）内形成有与通孔（101a）连接的气体通孔（112）。
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