公开(公告)号：KR100454505B1

公开(公告)日：2004-10-28

申请号：KR1020020050124

申请日：2002-08-23

Applicant: 한국전자통신연구원

Inventor： 주철원 ,  이경호 ,  민병규 ,  김성일 ,  이종민 ,  남은수 ,  강영일

IPC: C25D7/12

Abstract: PURPOSE: An electroplating device is provided which further improves uniformity of plating thickness by changing a member for resting an object to be plated into an electrode ring and constructing the electrode ring in an inclined shape so that bubbles generated from the surface of wafer that is the object to be plated are easily removed. CONSTITUTION: The electroplating device comprises a plating pot(100) which forms an external appearance, and in which a plating solution is contained; a metal box(110) positioned inside the plating pot and formed of the same metal as plating metal; an inclined electrode ring(120) which is positioned oppositely to the metal box in the plating pot, and on which an object to be plated is rested; a metal box fixing frame(140) for fixing the metal box; an electrode ring fixing frame(130) for fixing the inclined electrode ring; and power supply terminals(150,160) connected to the metal box and inclined electrode ring, wherein a wafer holder(170) is attached to the inclined electrode ring so that a wafer i.e., the object to be plated is rested on the wafer holder, wherein a chemical resistant material such as Teflon and polyethylene is coated on the surface of the metal box fixing frame and electrode ring fixing frame, and wherein the power supply terminals are connected to the metal box and inclined electrode ring through an inner part of the metal box fixing frame and electrode ring fixing frame.

Abstract translation: 目的：提供一种电镀装置，其通过改变用于将待电镀物体放置到电极环中的构件并且以倾斜形状构造电极环以使得从晶片表面产生的气泡 被镀物体很容易被去除。 构成：电镀装置包括形成外观并且包含电镀液的电镀锅（100） 金属盒（110），所述金属盒（110）定位在所述电镀锅内并且由与电镀金属相同的金属形成; 一个倾斜的电极环（120），该电极环与电镀锅中的金属盒相对地定位，并且在其上放置待电镀的物体; 金属盒固定框架（140），用于固定金属盒; 用于固定倾斜电极环的电极环固定框架（130） 和连接到所述金属盒和倾斜电极环的电源端子（150,160），其中晶片保持器（170）附接到所述倾斜电极环，使得晶片，即待镀物体放置在晶片保持器上，其中 在金属盒固定框架和电极环固定框架的表面涂覆有特氟隆，聚乙烯等耐化学性材料，其中，电源端子通过金属盒内部与金属盒和倾斜电极环连接 固定框架和电极环固定框架。

公开(公告)号：KR1020030030526A

公开(公告)日：2003-04-18

申请号：KR1020010062698

申请日：2001-10-11

Applicant: 한국전자통신연구원

Inventor： 주철원 ,  김성진 ,  백규하 ,  이희태 ,  이상균 ,  박성수

IPC: C25D17/06

Abstract: PURPOSE: A plating apparatus having electrode ring is provided to form a plating film having a uniformed thickness by adhering the electrode ring to the upper end of a plating tank so that an electric field is uniformly distributed on the surface of wafers during electroplating. CONSTITUTION: The plating apparatus comprises a plating tank; a plural first polarity contact point rods and a second polarity contact point rod formed on the plating tank; a loop shaped electrode ring(200) which is connected to the plural first polarity contact point rods, and on the inner surface of which a plurality of stepped projections(220) are formed so that the bodies to be plated are rested on the stepped projections with the circumference of the edge of various bodies to be plated having different size being contacted with the plurality of stepped projections(220), wherein the plating apparatus further comprises a metal box arranged at the lower part of the electrode ring to be connected to the second polarity contact point rod; and a sprayer arranged at the lower part of the metal box to spray a plating solution, wherein the plating tank comprises first plating tank on which the electrode ring and metal box are mounted, and second plating tank on which the sprayer is mounted, the first and second plating tanks are separately connected to each other, wherein the plating apparatus further comprises a plating tank of which outer wall covers the plating tank, and the upper part of which is opened, and a lid installed to open or close an opening part of the plating tank outer wall, wherein a power supply terminal connected to the first and second polarity contact point rods is installed on the lower surface of the lid, wherein the residual surface of the electrode ring is coated with a chemical resistant coating material(210) except a surface on which the bodies to be plated are rested and supported and a part of the electrode ring which comes in contact with the first polarity contact point rods, and wherein the coating material(210) is Teflon or polyethylene.

Abstract translation: 目的：提供具有电极环的电镀装置，通过将电极环粘附到电镀槽的上端，使电场在电镀期间在晶片表面均匀分布，形成均匀厚度的镀膜。 构成：电镀装置包括电镀槽; 形成在镀槽上的多个第一极性接触点棒和第二极性接触点棒; 连接到多个第一极性接触点棒的环形电极环（200），并且在其内表面上形成有多个台阶突起（220），使得被电镀的体被放置在台阶突起 其特征在于，具有不同尺寸的不同体的边缘的周缘与多个台阶突起（220）接触，其中，所述电镀装置还包括布置在所述电极环的下部的金属盒， 第二极接触点棒; 以及布置在所述金属盒的下部以喷射电镀液的喷雾器，其中所述镀槽包括安装有所述电极环和金属盒的第一镀槽和安装所述喷雾器的第二镀槽，所述第一镀槽 并且第二电镀槽彼此分离连接，其中，所述电镀装置还包括电镀槽，所述电镀槽的外壁覆盖所述镀槽，并且其上部被打开;以及盖，其安装成打开或关闭所述电镀槽的开口部 电镀槽外壁，其中连接到第一和第二极性接触点杆的电源端子安装在盖的下表面上，其中电极环的残余表面涂覆有耐化学腐蚀涂层材料（210） 除了要被电镀的体被放置和支撑的表面和与第一极性接触点接触的电极环的一部分之外，其中， 涂层材料（210）是聚四氟乙烯或聚乙烯。

公开(公告)号：KR100373398B1

公开(公告)日：2003-02-25

申请号：KR1019990041941

申请日：1999-09-30

Applicant: 한국전자통신연구원

Inventor： 주철원 ,  이영민 ,  이상복 ,  박성수 ,  송민규

IPC: H01L27/10

Abstract: PURPOSE: A multichip module substrate in which a built-in passive device is contained, as well as a method for manufacturing the substrate, is provided to realize a reduction in size of the substrate. CONSTITUTION: The substrate for a multichip module includes the built-in passive device such as a resistor, a capacitor and/or an inductor formed therein. To manufacture the substrate, the first insulating layer(11) is formed on a base substrate(10). The first seed metal layer(12) and the first main metal layer(13) are then stacked on the first insulating layer(11) to form the first metal layer(14). Next, the second insulating layer(15) having via holes is formed on the first metal layer(14), and the resistor(18) is then selectively formed thereon. Thereafter, the second metal layer(22) composed of the second seed and main metal layers(19,21) is formed on the second insulating layer(15), so that the capacitor is constituted by the first and second metal layers(14,22) and the second insulating layer(15). Then, the inductor is formed by the second metal layer(22), the third insulating layer(23) and the third metal layer(27).

Abstract translation: 目的：提供一种其中包含内置无源器件的多芯片模块基板以及用于制造基板的方法，以实现基板尺寸的减小。 构成：用于多芯片模块的基板包括内置的无源器件，例如形成在其中的电阻器，电容器和/或电感器。 为了制造基板，在基底基板（10）上形成第一绝缘层（11）。 然后将第一种金属层（12）和第一主金属层（13）堆叠在第一绝缘层（11）上以形成第一金属层（14）。 接着，在第一金属层（14）上形成具有通孔的第二绝缘层（15），然后在其上选择性地形成电阻器（18）。 之后，在第二绝缘层（15）上形成由第二晶种和主金属层（19,21）构成的第二金属层（22），使得电容器由第一和第二金属层（14， 22）和第二绝缘层（15）。 然后，电感器由第二金属层（22），第三绝缘层（23）和第三金属层（27）形成。

公开(公告)号：KR1020020054205A

公开(公告)日：2002-07-06

申请号：KR1020000083173

申请日：2000-12-27

Applicant: 한국전자통신연구원

Inventor： 김성진 ,  주철원 ,  백규하 ,  박성수 ,  이희태 ,  송민규

IPC: H01L21/60

Abstract: PURPOSE: A method for fabricating a bump is provided to minimize stress generated by the difference of a thermal expansion coefficient between a chip and a substrate, by forming the bump of a high aspect ratio. CONSTITUTION: Photoresist is coated several times to form a relatively thick photoresist. An exposure and development process is selectively performed regarding the photoresist to form a plurality of vias. A bump material is plated on the via. The photoresist is stripped. The plated bump material is reflowed to a spherical bump by a reflow method.

Abstract translation: 目的：提供一种用于制造凸块的方法，通过形成高纵横比的凸块来最小化由芯片和基板之间的热膨胀系数的差异产生的应力。 构成：将光致抗蚀剂涂覆数次以形成相对厚的光致抗蚀剂。 选择性地对光致抗蚀剂进行曝光和显影处理以形成多个通孔。 凸块材料镀在通孔上。 剥离光致抗蚀剂。 电镀凸块材料通过回流法回流到球形凸块。

公开(公告)号：KR1020010075962A

公开(公告)日：2001-08-11

申请号：KR1020000002917

申请日：2000-01-21

Applicant: 한국전자통신연구원

Inventor： 이영민 ,  이상복 ,  주철원 ,  박성수

IPC: H01L23/48

CPC classification number: H01L2224/10

Abstract: PURPOSE: A method for manufacturing a package applying a redistribution metallic wiring technology is provided to apply improved redistribution metallic wiring technology and to reduce manufacturing steps. CONSTITUTION: The method for manufacturing the package includes following steps. At first, a substrate for forming a device and a bonding pad is provided. Then, the first isolation layer(23) exposing the bonding pad is formed on an overall structure. At third, a redistribution metallic wire seed layer is formed along with the surface of the over the all surface. The, the first photosensitive pattern is formed on the redistribution metallic wire seed. Then, the redistributed metallic wiring is formed by an electric chemical vaporization on the redistributed metallic wiring seed layer. Then, the first photosensitive pattern is removed. At seventh, the second photosensitive pattern for defining a solder ball pad is formed on the overall structure. Then, a solder ball pad is formed on the exposed redistributed metallic wiring. At ninth, the second photosensitive pattern and the exposed redistributed metallic wiring seed layer is removed. At tenth, the second isolation layer is formed. Then, the second isolation layer is chemically-mechanically polished. Then, a solder ball(27) is formed on the solder ball pad.

Abstract translation: 目的：提供一种应用再分布金属布线技术的封装的制造方法，以应用改进的再分布金属布线技术并减少制造步骤。 构成：制造包装的方法包括以下步骤。 首先，提供用于形成装置的基板和接合焊盘。 然后，在整个结构上形成露出焊盘的第一隔离层（23）。 第三，再分布金属线种子层与所有表面的表面一起形成。 第一感光图案形成在再分布金属线种子上。 然后，通过在再分布的金属布线种子层上的电化学蒸发形成再分布的金属布线。 然后，去除第一感光图案。 第七，在整个结构上形成用于限定焊球垫的第二感光图案。 然后，在暴露的再分布金属布线上形成焊球垫。 第九，除去第二感光图案和暴露的再分布的金属布线籽晶层。 第十，形成第二隔离层。 然后，第二隔离层被化学机械抛光。 然后，在焊锡球焊盘上形成焊球（27）。

公开(公告)号：KR1020010020083A

公开(公告)日：2001-03-15

申请号：KR1019990041941

申请日：1999-09-30

Applicant: 한국전자통신연구원

Inventor： 주철원 ,  이영민 ,  이상복 ,  박성수 ,  송민규

IPC: H01L27/10

Abstract: PURPOSE: A multichip module substrate in which a built-in passive device is contained, as well as a method for manufacturing the substrate, is provided to realize a reduction in size of the substrate. CONSTITUTION: The substrate for a multichip module includes the built-in passive device such as a resistor, a capacitor and/or an inductor formed therein. To manufacture the substrate, the first insulating layer(11) is formed on a base substrate(10). The first seed metal layer(12) and the first main metal layer(13) are then stacked on the first insulating layer(11) to form the first metal layer(14). Next, the second insulating layer(15) having via holes is formed on the first metal layer(14), and the resistor(18) is then selectively formed thereon. Thereafter, the second metal layer(22) composed of the second seed and main metal layers(19,21) is formed on the second insulating layer(15), so that the capacitor is constituted by the first and second metal layers(14,22) and the second insulating layer(15). Then, the inductor is formed by the second metal layer(22), the third insulating layer(23) and the third metal layer(27).

Abstract translation: 目的：提供一种其中包含内置无源器件的多芯片模块衬底以及用于制造衬底的方法，以实现衬底尺寸的减小。 构成：用于多芯片模块的衬底包括诸如电阻器，电容器和/或其中形成的电感器的内置无源器件。 为了制造基板，第一绝缘层（11）形成在基底（10）上。 然后将第一种子金属层（12）和第一主金属层（13）堆叠在第一绝缘层（11）上以形成第一金属层（14）。 接下来，在第一金属层（14）上形成具有通孔的第二绝缘层（15），然后选择性地形成电阻（18）。 然后，在第二绝缘层（15）上形成由第二种子和主金属层（19,21）构成的第二金属层（22），使得电容器由第一和第二金属层（14， 22）和第二绝缘层（15）。 然后，电感器由第二金属层（22），第三绝缘层（23）和第三金属层（27）形成。

公开(公告)号：KR1020000015617A

公开(公告)日：2000-03-15

申请号：KR1019980035644

申请日：1998-08-31

Applicant: 한국전자통신연구원

Inventor： 이영민 ,  백종태 ,  이상복 ,  주철원 ,  박성수

IPC: H01F21/00

Abstract: PURPOSE: An adjustable inductor is provided to adjust values of an inductor on a circuit substrate, such as MCM, loading an electric element of an analog IC(Integrated Circuit) or an electric element of a super high frequency MMIC(Monolithic Microwave IC). CONSTITUTION: An inductor built in a circuit substrate, loading an electric element, connects a length adjusting wiring in several places having different length locations, in a main wiring of a standard-typed inductor circuit, connects the length adjusting wiring and the main wiring to a output terminal commonly in parallel, by using each connection wiring, and leaves one connection wiring, connected in parallel with an output terminal, and opens the rest of the connection wiring, electrically.

Abstract translation: 目的：提供可调电感器来调节电路基板上的电感值，例如MCM，加载模拟IC（集成电路）的电气元件或超高频MMIC（单片微波IC）的电气元件。 构成：在标准型电感器电路的主配线中，内置在电路基板中的电感器，装载电气元件，将长度调节布线连接在具有不同长度位置的多个位置，将长度调节布线和主布线连接到 通过并联连接的输出端子，通过使用每个连接布线，并且留下与输出端子并联连接的一个连接布线，并电连接其余的连接布线。

公开(公告)号：KR1020000013387A

公开(公告)日：2000-03-06

申请号：KR1019980032220

申请日：1998-08-07

Applicant: 한국전자통신연구원

Inventor： 주철원 ,  이영민 ,  이상복 ,  박성수

IPC: H01L21/28

Abstract: PURPOSE: A method for forming metal line of semiconductor device is provided to extend life of a semiconductor device by suppressing move of electron. CONSTITUTION: A first barrier metal layer, a metal layer, and a second barrier metal layer are deposed on upper surface of a silicon substrate. A metal line is patterned to form. And a metal spacer is formed on a side of the metal line. The metal spacer is formed by performing a plasma etch-back process after deposing TiW. The first barrier metal layer is formed 2000 Angstrom thick using TiW.

Abstract translation: 目的：提供一种用于形成半导体器件的金属线的方法，以通过抑制电子的移动来延长半导体器件的寿命。 构成：第一阻挡金属层，金属层和第二阻挡金属层被放置在硅衬底的上表面上。 图案化金属线。 并且在金属线的一侧上形成金属间隔物。 金属间隔物通过在除去TiW之后进行等离子体回蚀处理而形成。 使用TiW形成2000埃厚的第一阻挡金属层。

公开(公告)号：KR1020000002980A

公开(公告)日：2000-01-15

申请号：KR1019980024011

申请日：1998-06-25

Applicant: 한국전자통신연구원

Inventor： 주철원 ,  이영민 ,  이상복 ,  백종태 ,  김보우

IPC: H01L23/48

CPC classification number: H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/19107 ,  H01L2924/00014

Abstract: PURPOSE: A Quad Flat Package(QFP) is provided to minimize the number of electric source and grounding terminals for increasing the number of usable signal terminals. CONSTITUTION: A QFP comprises: an electric source wiring layer(44) and a grounding wiring layer(43); a conductive adhering layer(45) electrically connected to the electric source wiring layer and the grounding wiring layer; a thermal via unit(46) of the QFP electrically connected to the conductive adhering layer; a conductive metal layer(47) electrically connected to the thermal via unit of the QFP; and an electric source pattern and grounding pattern(49) of a printing circuit substrate electrically connected to the conductive metal layer through a connector unit.

Abstract translation: 目的：提供四平面封装（QFP），以最大限度地减少电源和接地端子数量，增加可用信号端子的数量。 构成：QFP包括：电源布线层（44）和接地布线层（43）; 电连接到电源布线层和接地布线层的导电粘合层（45）; 所述QFP的热通孔单元（46）电连接到所述导电粘附层; 电连接到所述QFP的热通孔单元的导电金属层（47）; 以及通过连接器单元电连接到导电金属层的印刷电路基板的电源图案和接地图案（49）。

公开(公告)号：KR100216517B1

公开(公告)日：1999-08-16

申请号：KR1019960056552

申请日：1996-11-22

Applicant: 주식회사 케이티 ,  한국전자통신연구원

Inventor： 주철원 ,  박흥옥 ,  이상복

IPC: H01L21/28 ,  H01L27/10

Abstract: 본 발명은 다중칩모듈 세라믹 기판(MCM-C)에서 가스 방출을 위한 전원층의 제조방법에 관한 것으로서, 종래 전원층은 층 전체를 금속과 유기용제로 조성된 금속-패이스트(metal paste)로 스크린 프린팅함으로써 프린팅후 열을 가하는 과정에서 유기용제로부터 가스가 발생하여 비아(via)를 채우고 있는 금속-패이스트에 압력이 작용하여 가스가 비아를 타고 올라가 윗부분은 가스로 인하여 비아와 비아 포획(capture)간의 연결상태가 끊겨지는 경우가 발생하여 전기적으로 단락(open) 현상이 발생할 수 있으므로 본 발명에서는 금속-패이스트에서 발생하는 가스의 양을 작게하여 가스가 비아에 가하는 압력을 낮추어 비아에서 일종의 기공현상을 제거함으로 인해 단락현상을 제거한다.