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    FLOATING POINT VECTOR COMPARISON INSTRUCTION WITH SELECTABLE OPTIONS
    112.
    发明专利
    FLOATING POINT VECTOR COMPARISON INSTRUCTION WITH SELECTABLE OPTIONS 未知

    公开(公告)号：ZA201903112B

    公开(公告)日：2021-04-28

    申请号：ZA201903112

    申请日：2019-05-17

    Applicant: IBM

    Inventor： BRADBURY JONATHAN ,  SCHWARZ ERIC ,  MUELLER SILVIA MELITTA ,  GSCHWIND MICHAEL KARL ,  OLSSON BRETT

    Abstract: An instruction to perform a comparison of a first value and a second value is executed. Based on a control of the instruction, a compare function to be performed is determined. The compare function is one of a plurality of compare functions configured for the instruction, and the compare function has a plurality of options for comparison. A compare option based on the first value and the second value is selected from the plurality of options defined for the compare function, and used to compare the first value and the second value. A result of the comparison is then placed in a select location, the result to be used in processing within a computing environment.

    DECIMAL SHIFT AND DIVIDE INSTRUCTION
    113.
    发明专利
    DECIMAL SHIFT AND DIVIDE INSTRUCTION 未知

    公开(公告)号：ZA201902291B

    公开(公告)日：2021-04-28

    申请号：ZA201902291

    申请日：2019-04-11

    Applicant: IBM

    Inventor： BRADBURY JONATHAN ,  COPELAND REID ,  MUELLER SILVIA MELITTA ,  SCHWARZ ERIC ,  CARLOUGH STEVEN

    Abstract: An instruction to perform a shift and divide operation is executed. The executing includes shifting a value in a specified direction by a selected amount to provide a dividend, the selected amount being user-defined. The dividend is divided by a divisor to obtain a quotient. At least a subset of the quotient is selected as a result. The result is to be used in processing within the computing environment.

    SPILLING TEMPORARY RESULTS FOR ACCOMMODATION OF MEMORY BOUNDARIES
    114.
    发明专利
    SPILLING TEMPORARY RESULTS FOR ACCOMMODATION OF MEMORY BOUNDARIES 未知

    公开(公告)号：CA3131257A1

    公开(公告)日：2020-09-03

    申请号：CA3131257

    申请日：2020-02-27

    Applicant: IBM

    Inventor： KURUP GIRISH GOPALA ,  KLEIN MATTHIAS ,  SOFIA ANTHONY THOMAS ,  BRADBURY JONATHAN ,  MISHRA ASHUTOSH ,  JACOBI CHRISTIAN ,  BHATTACHARJEE DEEPANKAR

    IPC: H03M7/40

    Abstract: An aspect includes a system architecture that includes a processing unit, an accelerator, a main source buffer, a main target buffer, and a memory block. The main source buffer stores a first part of a source symbol received from an external source. The main target buffer stores an output symbol received from the accelerator. The memory block includes an overflow source buffer that stores the first part of the source symbol received from the main source buffer. The accelerator fetches the first part of the source symbol stored in the overflow source buffer and a second part of the source symbol stored in the main source buffer, and converts the first and second parts of the source symbol together into the output symbol. The second part of the source symbol includes a part of the source symbol not included in the first part of the source symbol.

    HANDLING AN INPUT/OUTPUT STORE INSTRUCTION
    115.
    发明专利
    HANDLING AN INPUT/OUTPUT STORE INSTRUCTION 未知

    公开(公告)号：CA3127852A1

    公开(公告)日：2020-08-06

    申请号：CA3127852

    申请日：2020-01-14

    Applicant: IBM

    Inventor： RAISCH CHRISTOPH ,  KRAEMER MARCO ,  LEHNERT FRANK ,  KLEIN MATTHIAS ,  BRADBURY JONATHAN ,  JACOBI CHRISTIAN ,  BELMAR BRENTON ,  DRIEVER PETER

    IPC: G06F9/30 ,  G06F13/00 ,  G06F13/20

    Abstract: A data processing system (210) and a method for handling an input/output store instruction (30), comprising a system nest (18) communicatively coupled to at least one input/output bus (22) by an input/output bus controller (20). The data processing system (210) further comprises at least a data processing unit (216) comprising a core (12), a system firmware (10) and an asynchronous core-nest interface (14). The data processing unit (216) is communicatively coupled to the system nest (18) via an aggregation buffer (16). The system nest (18) is configured to asynchronously load from and/or store data to an external device (214) which is communicatively coupled to the input/output bus (22). The data processing unit (216) is configured to complete the input/output store instruction (30) before an execution of the input/output store instruction (30) in the system nest (18) is completed.

    Perform sign operation decimal instruction
    117.
    发明专利
    Perform sign operation decimal instruction 未知

    公开(公告)号：AU2017333837B2

    公开(公告)日：2020-07-16

    申请号：AU2017333837

    申请日：2017-09-22

    Applicant: IBM

    Inventor： COPELAND REID ,  MUELLER SILVIA MELITTA ,  BRADBURY JONATHAN ,  SLEGEL TIMOTHY

    IPC: G06F9/30

    Abstract: An instruction to perform a sign operation of a plurality of sign operations configured for the instruction. The instruction is executed, and the executing includes selecting at least a portion of an input operand as a result to be placed in a select location. The selecting is based on a control of the instruction, in which the control indicates a user-defined size of the input operand to be selected as the result. A sign of the result is determined based on a plurality of criteria, including a value of the result, obtained based on the control of the instruction, having a first particular relationship or a second particular relationship with respect to a selected value. The result and the sign are stored in the select location to provide a signed output to be used in processing within the computing environment.

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