公开(公告)号：EP1113450B1

公开(公告)日：2007-04-25

申请号：EP99830825.8

申请日：1999-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Zammattio, Matteo ,  Motta, Ilaria ,  Micheloni, Rino ,  Golla, Carla

IPC: G11C16/30 ,  G11C5/14

CPC classification number: G11C16/30 ,  G11C5/145

公开(公告)号：EP1420415A3

公开(公告)日：2007-02-28

申请号：EP03104130.4

申请日：2003-11-10

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Ravasio, Roberto

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: A circuit (115,145,150) for programming a non-volatile memory device (100) having a plurality of memory cells (105) is proposed. The circuit includes a plurality of driving elements (115) each one for applying a program pulse to a selected memory cell to be programmed, the driving elements being suitable to be supplied by a power supply unit (120,125), and control means (145,150) for controlling the driving elements; the control means includes means (150,205) for determining a residual capacity of the power supply unit, and selecting means (145) for selectively enabling the driving elements according to the residual capacity.

公开(公告)号：EP1750278A1

公开(公告)日：2007-02-07

申请号：EP06115106.4

申请日：2006-06-07

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Micheloni, Rino

IPC: G11C11/56

CPC classification number: G11C16/10 ,  G11C11/5628

Abstract: When the threshold voltage of a cell of a four-level FLASH memory device, that includes an array of singularly addressable preliminarily erased memory cells each capable of storing a two-bit datum, is verified to have reached the desired distribution, the cell is read using a test read voltage smaller than or equal to the program voltage. In this situation the voltage V S on the source node is surely negligible and the programmed state of the cell may be correctly verified.
A novel architecture of a page buffer is also provided.

Abstract translation: 当一台四电平快闪存储器装置的单元的阈值电压，没有包括在单独可寻址的预先擦除的存储器单元每个都能够存储一个两比特的日期的阵列，被验证为已达到期望的分布，该单元被读 使用测试读取电压小于或等于所述编程电压。 在这种情况下在源节点上的电压V S是可靠地忽略不计，单元的编程状态可被正确验证。 因此，提供的页缓冲器的一种新颖的体系结构。

公开(公告)号：EP1748446A1

公开(公告)日：2007-01-31

申请号：EP05106975.5

申请日：2005-07-28

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Micheloni, Rino ,  Crippa, Luca ,  Ravasio, Roberto

IPC: G11C11/56

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3436 ,  G11C2211/5621 ,  G11C2211/5642

Abstract: A method for programming an electrically programmable memory (100) is provided. The electrically programmable memory includes a plurality of memory cells (110) arranged in individually-selectable memory cell sets each including at least one memory cell, a plurality of distinct memory cell programming states (201, 202, 203, 204) corresponding to a number N >=2 of data bits storable in each memory cell. The data bits include at least a first data bits group (LSB) and a second data bits group (MSB); the first data bits groups and, respectively, the second data bits groups stored in the memory cells of one of said individually-selectable memory cell sets form at least a first memory page and a second memory page, respectively, the first and second memory pages being individually addressable.
The programming method comprises:
- causing the memory cells of a selected memory cells set to be brought into a predetermined, starting programming state (201);
- receiving a target value for the first data bits groups of the memory cells of the selected memory cells set;
- receiving a target value for the second data bits groups of the memory cells of the selected memory cells set;
- after having received the target values of both the first and the second data bits groups, applying to the memory cells of the selected memory cells set a programming sequence (350) adapted to cause the memory cells of the selected memory cells sets to be brought into a target programming state (201,202,203,204) jointly determined by the target values of the first and second data bits groups.

Abstract translation: 提供了一种用于编程电可编程存储器（100）的方法。 电可编程存储器包括布置在可单独选择的存储单元组中的多个存储单元（110），每个存储单元组包括至少一个存储单元，多个不同的存储单元编程状态（201,202,203,204） N> = 2可存储在每个存储单元中的数据位。 数据位包括至少第一数据位组（LSB）和第二数据位组（MSB）; 第一数据位组和分别存储在所述可单独选择的存储单元组之一的存储单元中的第二数据位组分别形成至少第一存储器页和第二存储器页，第一和第二存储器页 单独寻址。 编程方法包括： - 使所设置的选定存储单元的存储单元进入预定的开始编程状态（201）; - 接收所选存储单元组的存储单元的第一数据位组的目标值; - 接收所选存储单元组的存储单元的第二数据位组的目标值; - 在已经接收到第一和第二数据位组之间的目标值之后，向所选择的存储单元的存储单元施加设置适于使所选择的存储单元组的存储单元被带入的编程序列（350） 转换为由第一和第二数据位组的目标值共同确定的目标编程状态（201,202,203,204）。

公开(公告)号：EP1748443A1

公开(公告)日：2007-01-31

申请号：EP05106973.0

申请日：2005-07-28

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Micheloni, Rino

IPC: G11C5/02 ,  G11C11/56

CPC classification number: G11C11/5628 ,  G11C5/025 ,  G11C11/5642 ,  G11C2211/5642

Abstract: A memory device (100) is provided. The memory device includes a matrix (105) of memory cells (110) adapted to store data and arranged in a plurality of bit lines (BLe, BLo), the bit lines extending along a first direction (Y); a page buffer (130) adapted to interface the matrix with a downstream circuitry (125c, 140), the page buffer comprising a plurality of read/program units (205(i)). Each read/program unit is associated with and operatively couplable to at least one bit line. The memory device further includes at least two groups each including at least two respective read/program units, wherein the read/program units of a generic one of said groups are generically aligned along the first direction. The at least two groups are generically aligned along a second direction (X) transversal to the first direction. The memory device further includes at least one signal track (BITOUT) associated with each one of said groups for conveying signals corresponding to data read from the memory cells to the downstream circuitry are provided. Said at least one signal track is shared by the at least two read/program units of the corresponding group. The memory device further includes means (410) for selectively assigning the at least one signal track to one of the associated read/program unit at a time among the at least two read/program units of the group associated with said signal track.

Abstract translation: 提供存储器件（100）。 存储器件包括适于存储数据并且布置在沿着第一方向（Y）延伸的位线的多个位线（BLe，BLo））中的存储器单元（110）的矩阵（105）。 适于将矩阵与下游电路（125c，140）接口的页缓冲器（130），所述页缓冲器包括多个读/程序单元（205（i））。 每个读取/编程单元与至少一个位线相关联并可操作地耦合到至少一个位线。 存储器件还包括至少两组，每组包括至少两个相应的读/写单元，其中所述组中的通用一个的读/程单元沿第一方向一般对准。 所述至少两个组沿着沿着所述第一方向横向的第二方向（X）被一般排列。 存储器装置还包括与所述组中的每一个相关联的至少一个信号轨道（BITOUT），用于将对应于从存储器单元读取的数据传送到下游电路的信号。 所述至少一个信号轨道由对应组的至少两个读/写单元共享。 存储器件还包括用于在与所述信号轨道相关联的组的至少两个读取/编程单元中的一个时间将至少一个信号轨迹选择性地分配给相关联的读取/编程单元中的一个的装置（410）。

公开(公告)号：EP1746605A1

公开(公告)日：2007-01-24

申请号：EP05106782.5

申请日：2005-07-22

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Crippa, Luca ,  Missiroli, Chiara ,  Micheloni, Rino

IPC: G11C16/26 ,  G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/26

Abstract: A reading method of a NAND memory device including the steps of: first connecting a first end terminal (12a) of a stack (12) of cells (3, 3', 3") to a reference line (13); second connecting a second end terminal (12b) of the stack (12) of cells (3, 3', 3") to a respective bitline (10); charging the bitline (10) to a predetermined bitline read voltage (V DR ), wherein one of the steps of first connecting and second connecting is carried out before charging the bitline (10) and the other of the steps of first connecting and second connecting is carried out after charging the bitline (10). An order of carrying out the steps of first connecting and second connecting is determined based on an address (MSB; AL2) of a selected cell (3', 3") .

Abstract translation: 一种NAND存储装置的读取方法，包括以下步骤：首先将单元（3,3'，3“）的堆叠（12）的第一端子（12a）连接到参考线（13）;第二连接 单元（3,3'，3“）的堆叠（12）的第二端子（12b）到相应的位线（10）; 将位线（10）充电到预定的位线读取电压（V DR），其中在对位线（10）充电之前执行第一连接和第二连接的步骤之一，并且第一连接和第二连接的另一个步骤 在对位线（10）充电之后进行。 基于选择的单元（3'，3“）的地址（MSB; AL2）确定执行第一连接和第二连接步骤的顺序。

公开(公告)号：EP1612949A1

公开(公告)日：2006-01-04

申请号：EP04425485.2

申请日：2004-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Marelli, Alessia ,  Ravasio, Roberto ,  Micheloni, Rino

IPC: H03M13/15 ,  G06F11/10

CPC classification number: H03M13/152 ,  H03M13/1575 ,  H03M13/3707 ,  H03M13/6502

Abstract: The invention relates to a method and system for correcting errors in multilevel memories using binary BCH codes. The number of errors is estimated by analyzing the syndrome components (5). If the number of estimated errors is one, then simple decoding for a Hamming code is performed. Otherwise, conventional decoding of the BCH code is carried out (2,3). This avoids the computation of the error locator polynomial and its roots in the presence of only one error and, thus, reduces the average decoding complexity.

Abstract translation: 本发明涉及一种使用二进制BCH码对多层存储器中的错误进行校正的方法和系统。 通过分析综合征成分估计误差数（5）。 如果估计误差的数量为1，则执行汉明码的简单解码。 否则，执行BCH码的常规解码（2,3）。 这避免了在仅存在一个错误的情况下计算错误定位器多项式及其根，并因此降低平均解码复杂度。

公开(公告)号：EP1126372B1

公开(公告)日：2005-05-18

申请号：EP00830103.8

申请日：2000-02-14

Applicant: STMicroelectronics S.r.l.

Inventor： Manstretta, Alessandro ,  Micheloni, Rino ,  Pierin, Andrea ,  Yero, Emilio

IPC: G06F11/20

CPC classification number: G11C29/70

公开(公告)号：EP1420415A2

公开(公告)日：2004-05-19

申请号：EP03104130.4

申请日：2003-11-10

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Ravasio, Roberto

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: A circuit (115,145,150) for programming a non-volatile memory device (100) having a plurality of memory cells (105) is proposed. The circuit includes a plurality of driving elements (115) each one for applying a program pulse to a selected memory cell to be programmed, the driving elements being suitable to be supplied by a power supply unit (120,125), and control means (145,150) for controlling the driving elements; the control means includes means (150,205) for determining a residual capacity of the power supply unit, and selecting means (145) for selectively enabling the driving elements according to the residual capacity.

Abstract translation: 提出了一种用于对具有多个存储单元（105）的非易失性存储器件（100）进行编程的电路（115,145,150）。 电路包括多个驱动元件（115），每个驱动元件（115）用于将编程脉冲施加到要被编程的所选择的存储器单元，所述驱动元件适于由电源单元（120,125）提供;以及控制装置（145,150） 用于控制驱动元件; 所述控制装置包括用于确定所述电源单元的剩余容量的装置（150,205），以及用于根据所述剩余容量选择性地启用所述驱动元件的选择装置（145）。

公开(公告)号：EP1031991B1

公开(公告)日：2004-04-28

申请号：EP99830108.9

申请日：1999-02-26

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Campardo, Giovanni

IPC: G11C11/56

CPC classification number: G11C11/5642