中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

304 records (took 0.019 seconds)

    Three-dimensional multi-layer circuit structure and method for forming the same
    122.
    发明授权
    Three-dimensional multi-layer circuit structure and method for forming the same 失效
    三维多层电路结构及其形成方法

    公开(公告)号：US5738797A

    公开(公告)日：1998-04-14

    申请号：US649377

    申请日：1996-05-17

    Applicant: Robert E. Belke, Jr. ,  Michael G. Todd ,  Andrew Z. Glovatsky ,  Alice D. Zitzmann

    Inventor： Robert E. Belke, Jr. ,  Michael G. Todd ,  Andrew Z. Glovatsky ,  Alice D. Zitzmann

    IPC: C23F1/02 ,  H05K3/00 ,  H05K3/06 ,  H05K3/20 ,  H05K3/46 ,  B44C1/22 ,  C23F1/00

    CPC classification number: H05K3/4685 ,  C23F1/02 ,  H05K3/062 ,  H05K3/205 ,  H05K2201/0361 ,  H05K2201/0394 ,  H05K2201/09018 ,  H05K2201/09118 ,  H05K2203/0152 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K3/0014

    Abstract: A three dimensional multi-layer circuit structure is formed by partially etching a foil having a coating. A pre-circuit is formed by providing a metal foil, applying a photodefinable photoresist to each side of the metal foil, selectively exposing and developing the photoresist leaving exposed areas and unexposed areas and, plating the unexposed areas with a second metal. The pre-circuit is placed in an etching solution and removed after the etching solution partially etches the metal foil to undercut the second metal. The partially etched pre-circuit is then bent into a predetermined shape. The partially etched pre-circuit is then inserted into a mold cavity so that at least one surface of the circuit structure is adjacent to the mold. The mold is filled with a polymer resin so that the polymer resin encapsulates at least a portion of the partially etched pre-circuit and substantially fills the undercut. The molded circuit structure is then removed from the mold and the metallic foil is further etched to complete the forming of the circuit.

    Abstract translation: 通过部分蚀刻具有涂层的箔形成三维多层电路结构。 通过提供金属箔，在金属箔的每一侧上施加可光限定的光致抗蚀剂，选择性地暴露和显影光致抗蚀剂以形成暴露区域和未曝光区域，以及用第二金属镀覆未曝光区域来形成预制电路。 将预电路放置在蚀刻溶液中，并且在蚀刻溶液部分蚀刻金属箔以切割第二金属之后移除。 然后将部分蚀刻的预循环弯曲成预定的形状。 然后将部分蚀刻的预制电路插入模腔中，使得电路结构的至少一个表面与模具相邻。 模具填充有聚合物树脂，使得聚合物树脂封装部分蚀刻的预循环的至少一部分并且基本上填充底切。 然后将模制电路结构从模具中取出，并且金属箔被进一步蚀刻以完成电路的形成。

    Electroformed chemically milled probes for chip testing
    123.
    发明授权
    Electroformed chemically milled probes for chip testing 失效
    电铸化学研磨探针，用于芯片测试

    公开(公告)号：US5027062A

    公开(公告)日：1991-06-25

    申请号：US364876

    申请日：1989-06-12

    Applicant: William P. Dugan ,  Marvin R. Johnson

    Inventor： William P. Dugan ,  Marvin R. Johnson

    IPC: G01R1/067 ,  G01R1/073 ,  H05K3/06 ,  H05K3/20 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

    CPC classification number: H05K3/4007 ,  G01R1/07314 ,  G01R1/06711 ,  G01R3/00 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/1476 ,  H05K3/062 ,  H05K3/064 ,  H05K3/205 ,  H05K3/423 ,  H05K3/4647

    Abstract: A method for manufacturing a probe test structure for microcircuits utilizes a multiple coating method in conjunction with a novel double-cell electroplating apparatus having a relatively high-resistance ion path between the cells. Photoresist is applied to both sides of a copper foil, copper posts are electroformed onto selected areas of one side of the foil through image hole patterns, the remaining photoresist is stripped away, polyimide prepreg is laminated to the post side of the foil, the copper posts are exposed by sanding, photoresist is reapplied to both sides of the sanded remainder, additional copper is electroformed on each post through image hole patterns in the post side of the photoresist, the foil on the side opposite the posts is chemically milled to provide leads integral with each post using appropriate masking techniques and, finally, all of the remaining photoresist is removed to leave the desired test probe set. In a second embodiment, nickel plating is added over the copper to achieve selective etching, permitting processing of both sides of the copper foil simultaneously.

    Abstract translation: 一种用于制造微电路探针测试结构的方法利用多层涂覆方法与新颖的双电池电镀设备相结合，该双电池电镀设备在电池之间具有相对较高的电阻离子路径。 将光刻胶施加到铜箔的两面，铜柱通过图像孔图案电铸成箔的一侧的选定区域，残留的光致抗蚀剂被剥离，聚酰亚胺预浸料层压到箔的后侧，铜 通过砂光曝光柱，将光致抗蚀剂重新施加到磨砂剩余部分的两侧，通过在光致抗蚀剂的后侧中的图像孔图案，在每个柱上电铸附加的铜，将化学铣削在柱的相对侧上的箔以提供引线 使用适当的掩蔽技术与每个柱整体，最后，除去所有剩余的光致抗蚀剂以留下所需的测试探针组。 在第二实施例中，在铜上添加镍电镀以实现选择性蚀刻，从而允许铜箔的两面同时加工。

    Electroformed chemically milled probes for chip testing
    124.
    发明授权
    Electroformed chemically milled probes for chip testing 失效
    电铸化学研磨探针，用于芯片测试

    公开(公告)号：US4878294A

    公开(公告)日：1989-11-07

    申请号：US208907

    申请日：1988-06-20

    Applicant: William P. Dugan ,  Marvin R. Johnson

    Inventor： William P. Dugan ,  Marvin R. Johnson

    IPC: G01R1/067 ,  G01R1/073 ,  H05K3/06 ,  H05K3/20 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

    CPC classification number: H05K3/4007 ,  G01R1/07314 ,  G01R1/06711 ,  G01R3/00 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/1476 ,  H05K3/062 ,  H05K3/064 ,  H05K3/205 ,  H05K3/423 ,  H05K3/4647 ,  Y10T29/49165

    Abstract: A method for manufacturing a probe test structure for microcircuits utilizes a multiple coating method in conjunction with a novel double-cell electroplating apparatus having a relatively high-resistance ion path between the cells. Photoresist is applied to both sides of a copper foil, copper posts are electroformed onto selected areas of one side of the foil through image hole patterns, the remaining photoresist is stripped away, polyimide prepreg is laminated to the post side of the foil, the copper posts are exposed by sanding, photoresist is reapplied to both sides of the sanded remainder, additional copper is electroformed on each post through image hole patterns in the post side of the photoresist, the foil on the side opposite the posts is chemically milled to provide leads integral with each post using appropriate masking techniques and, finally, all of the remaining photoresist is removed to leave the desired test probe set. In a second embodiment, nickel plating is added over the copper to acheive selective etching, permitting processing of both sides of the copper foil simultaneously.

    Abstract translation: 一种用于制造微电路探针测试结构的方法利用多层涂覆方法与新颖的双电池电镀设备相结合，该双电池电镀设备在电池之间具有相对较高的电阻离子路径。 将光刻胶施加到铜箔的两面，铜柱通过图像孔图案电铸成箔的一侧的选定区域，残留的光致抗蚀剂被剥离，聚酰亚胺预浸料层压到箔的后侧，铜 通过砂光曝光柱，将光致抗蚀剂重新施加到磨砂剩余部分的两侧，通过在光致抗蚀剂的柱侧中的图像孔图案，在每个柱上电铸附加的铜，将化学铣削在柱的相对侧上的箔以提供引线 使用适当的掩蔽技术与每个柱整体，最后，除去所有剩余的光致抗蚀剂以留下所需的测试探针组。 在第二实施例中，通过铜上镀镍以进行选择性蚀刻，从而允许铜箔的两面同时加工。

    배선 기판의 제조 방법
    126.
    发明公开
    배선 기판의 제조 방법 失效
    生产电路板的工艺

    公开(公告)号：KR1020070120013A

    公开(公告)日：2007-12-21

    申请号：KR1020060110430

    申请日：2006-11-09

    Applicant: 후지쯔 가부시끼가이샤

    Inventor： 다카노겐지 ,  시바타무네카즈 ,  아라이카즈야 ,  가나이주니치 ,  스기모토가오루

    IPC: H05K3/46 ,  H05K3/06

    CPC classification number: H05K3/20 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/423 ,  H05K3/4682 ,  H05K2201/0361 ,  H05K2201/096 ,  H05K2203/0156 ,  H05K2203/0384 ,  H05K2203/1536 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A method for manufacturing a circuit board is provided to implement an LSI(Large Scale Integration) on the circuit board by planarizing a surface of the circuit board by burying a wiring pattern in an insulation layer. In a photolithography process, a third metal layer(65) of a 3-layer metal laminate(62) is etched to form a predetermined line pattern. A laminate electrically connected to a wiring pattern between layers through an insulation layer is formed on the wiring pattern by using a build-up process. The laminate is peeled from a base board between a first metal layer(63) and the base board. The first metal layer of the laminate is etched by using a second metal layer(64) as a barrier layer. The exposed second metal layer is etched.

    Abstract translation: 提供一种制造电路板的方法，通过将绝缘层中的布线图形掩埋而使电路板的表面平坦化，从而在电路板上实现LSI（大规模集成）。 在光刻工艺中，蚀刻三层金属层压板（62）的第三金属层（65）以形成预定的线图案。 通过使用积聚方法在布线图案上形成通过绝缘层电连接到层之间的布线图案的层压体。 层压体从基板在第一金属层（63）和基板之间剥离。 通过使用第二金属层（64）作为阻挡层来蚀刻层压体的第一金属层。 暴露的第二金属层被蚀刻。

    MULTILAYER WIRING ELEMENT HAVING PIN INTERFACE
    130.
    发明申请
    MULTILAYER WIRING ELEMENT HAVING PIN INTERFACE 审中-公开
    具有接口接口的多层接线元件

    公开(公告)号：WO2009005696A1

    公开(公告)日：2009-01-08

    申请号：PCT/US2008/007978

    申请日：2008-06-23

    Applicant: TESSERA, INC. ,  HABA, Belgacem

    Inventor： HABA, Belgacem

    IPC: H05K3/46

    CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/181 ,  H05K3/06 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2203/0384 ,  Y10T29/49144 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A method of forming contacts for an interconnection element (10), includes (a) joining a conductive element (16) to an interconnection element 10 having multiple wiring layers, (b) patterning the conductive element (16) to form conductive pins (20), and (c) electrically interconnecting the conductive pins (20) with conductive features of the interconnection element (10). A multiple wiring layer interconnection element (10) having an exposed pin interface, includes an interconnection element (10) having multiple wiring layers separated by at least one dielectric layer (24), the wiring layers including a plurality of conductive features exposed at a first face of the interconnection element (10), a plurality of conductive pins (20) protruding in a direction away from the first face, and metal features (22) electrically interconnecting the conductive features with the conductive pins (20).

    Abstract translation: 一种形成用于互连元件（10）的触点的方法包括：（a）将导电元件（16）接合到具有多个布线层的互连元件10上，（b）图案化导电元件（16）以形成导电引脚 ）和（c）将导电引脚（20）与互连元件（10）的导电特征电互连。 具有暴露的引脚接口的多重布线层互连元件（10）包括具有由至少一个介电层（24）隔开的多个布线层的互连元件（10），所述布线层包括多个导电特征 互连元件（10）的表面，沿远离第一面的方向突出的多个导电引脚（20）以及将导电特征与导电引脚（20）电连接的金属特征（22）。

Patent Agency Ranking