Data communications
    133.
    发明专利

    公开(公告)号:AU8609601A

    公开(公告)日:2002-04-02

    申请号:AU8609601

    申请日:2001-09-13

    Abstract: Control and/or observation of a plurality of devices, in particular consumer electronics devices, by a controller device with hypertext or hypermedia communication capabilities, such as a WAP-enabled mobile phone, preferably over a proximity bearer such as Bluetooth (RTM). Data can be sent from the controlled side to the controller side as well as from the controller side to the controlled side. Data flowing from the controlled side to the controller side may include data representing the operational status of the controlled device and/or data for programming the controller device to enable it to send control data to the controlled device for controlling the controlled device. The hypermedia data message generated by the controlled device may include hyperlinks or other menu options which may be dependent upon the current operational state of the controlled device, and which may be selected by the user of the controller, thereby causing the controller to send a control message to the controlled device.

    Data Communications
    134.
    发明专利

    公开(公告)号:GB0022474D0

    公开(公告)日:2000-11-01

    申请号:GB0022474

    申请日:2000-09-13

    Abstract: Control and/or observation of a plurality of devices, in particular consumer electronics devices, by a controller device with hypertext or hypermedia communication capabilities, such as a WAP-enabled mobile phone, preferably over a proximity bearer such as Bluetooth (RTM). Data can be sent from the controlled side to the controller side as well as from the controller side to the controlled side. Data flowing from the controlled side to the controller side may include data representing the operational status of the controlled device and/or data for programming the controller device to enable it to send control data to the controlled device for controlling the controlled device. The hypermedia data message generated by the controlled device may include hyperlinks or other menu options which may be dependent upon the current operational state of the controlled device, and which may be selected by the user of the controller, thereby causing the controller to send a control message to the controlled device.

    pilha de transações para dispositivos eletrônicos, incluindo memória não-volátil com ciclo de gravação limitado

    公开(公告)号:BRPI0611161A2

    公开(公告)日:2019-02-26

    申请号:BRPI0611161

    申请日:2006-04-28

    Inventor: CONCILIO MARIANO

    Abstract: "pilha de transações para dispositivos eletrônicos, incluindo memória não-volátil com ciclo de gravação limitado" a presente invenção se refere a uma pilha de transações ( 2) para dispositivos com memória de ciclo de gravação limitado, dita pilha de transações (2) deslizando no interior de um buffer de transações (1). após um evento de commit transaction (consignar transação) ou, alternativamente, begin transaction (iniciar transação), a pilha de transações ( 2) é realocada no interior do buffer de transações (1) e, conseqüentemente, alguns locais de memória no interior do buffer de transações ( 1) são liberados. os acessos à gravação para a memória de área não-volátil do buffer de transações ( 1) não se encontram concentrados no primeiro endereço, como ocorre na implementação padrão de uma pilha de transações, porém, são espalhados por todos os locais do buffer de transações (1).

    140.
    发明专利
    未知

    公开(公告)号:DE602006006990D1

    公开(公告)日:2009-07-09

    申请号:DE602006006990

    申请日:2006-06-28

    Abstract: A processor architecture (10) e.g. for multimedia applications, includes a plurality of processor clusters (18a, 18b) that provide a vectorial data processing capability. The processing elements in the processor clusters (18a, 18b) are configured to process both data with a given bit length N and data with bit lengths N/2, N/4, and so on according to a Single Instruction Multiple Data (SIMD) paradigm. A load unit (26) is provided for loading into the processor clusters (18a, 18b) data to be processed in the form of sets of more significant bits and less significant bits of operands to be processed according to a same instruction. An intercluster datapath (28) exchanges and/or merges data between the processor clusters (18a, 18b). The intercluster datapath (28) is scalable to activate selected ones of the processor clusters (18a, 18b), whereby the architecture (10) is adapted to operate simultaneously on SIMD, scalar and vectorial data. Preferably, the instruction subsystem (12) has instruction parallelism capability and the intercluster datapath (28) is configured for performing operations on e.g. 2*N data. Preferably, a data cache memory (34) is provided which is accessible either in a scalar mode or in a vectorial mode.

Patent Agency Ranking