-
公开(公告)号：KR1020100011291A
公开(公告)日：2010-02-03
申请号：KR1020080072438
申请日：2008-07-24
Applicant: 삼성전자주식회사
IPC: H01L27/146
CPC classification number: H01L27/14643 , B82Y20/00 , B82Y30/00 , H01L27/14625
Abstract: PURPOSE: An image sensor having a light focusing structure is provided to focus in on a wide photoelectric conversion area by including a metal nano dot on a submicron sized floating body. CONSTITUTION: A plurality of pixel units are arranged in an array shape. A pixel unit comprises a first area(112) and a second area(114) in which materials having different polarities are doped. A photoelectric conversion region(116) is formed between the first area and the second area. At least one metal nano-dot(120) focuses incoming light on the photoelectric conversion region. The metal nano-dot is arranged on the semiconductor layer(110).
Abstract translation: 目的：提供具有光聚焦结构的图像传感器，通过在亚微米尺寸的浮体上包括金属纳米点来聚焦在宽的光电转换区域上。 构成：多个像素单元被布置成阵列形状。 像素单元包括其中掺杂有不同极性的材料的第一区域（112）和第二区域（114）。 在第一区域和第二区域之间形成光电转换区域（116）。 至少一个金属纳米点（120）将入射光聚焦在光电转换区域上。 金属纳米点布置在半导体层（110）上。
-
公开(公告)号：KR1020090127047A
公开(公告)日：2009-12-09
申请号：KR1020090029057
申请日：2009-04-03
Applicant: 삼성전자주식회사
IPC: G02B6/42
Abstract: PURPOSE: A semiconductor device is provided to rapidly transmit data without loss or damage to the data by arranging at least one or more photoelectric modules between a central processing unit and a memory module. CONSTITUTION: A memory module is connected to a memory controller(10), and is mounted to a corresponding to socket. A first photoelectric module(12) is connected to the memory controller. One side of an optical channel is connected to the first photoelectric module. The other side of the optical channel is extended via the socket. At least one part of elements is mounted to a system board(8). A second photoelectric module is mounted to the socket, and is positioned between the optical channel and the memory module.
Abstract translation: 目的：提供一种半导体器件，用于通过在中央处理单元和存储器模块之间布置至少一个或多个光电模块来快速传输数据而不损失或损坏数据。 构成：存储器模块连接到存储器控制器（10），并被安装到相应的插座上。 第一光电模块（12）连接到存储器控制器。 光通道的一侧连接到第一光电模块。 光通道的另一侧通过插座延伸。 至少一部分元件安装到系统板（8）上。 第二光电模块安装到插座上，并且位于光通道和存储器模块之间。
-
公开(公告)号：KR1020090102262A
公开(公告)日：2009-09-30
申请号：KR1020080027592
申请日：2008-03-25
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C16/3409 , G11C16/344 , G11C16/3454
Abstract: PURPOSE: A method for operating a memory device is provided to implement a negative valid effect test voltage below 0 V while applying the voltage of 0V or more to a control gate of the memory cell. CONSTITUTION: A pre-program voltage is applied to a memory cell of an erase state(S110). The memory cell is pre-programmed to have a smaller threshold voltage distribution in comparison with the erase state. Whether the memory cell is pre-programmed is verified using the negative valid verification voltage(S130).
Abstract translation: 目的：提供一种用于操作存储器件的方法，以在0V以上的电压施加到存储器单元的控制栅极的情况下实现低于0V的负有效效应测试电压。 构成：将预编程电压施加到擦除状态的存储单元（S110）。 与擦除状态相比，存储器单元被预编程为具有较小的阈值电压分布。 使用负有效验证电压验证存储器单元是否被预编程（S130）。
-
公开(公告)号：KR1020090080634A
公开(公告)日：2009-07-27
申请号：KR1020080006501
申请日：2008-01-22
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5628 , G11C29/00 , G11C2216/14
Abstract: An apparatus and a method for programming a memory are provided to minimize area overhead by using a new multi level programming method when verifying an error of the data stored in the memory cell. A data storage(110) stores a data page. A first counter(130) generates index information by counting the number of cells with at least one reference threshold voltage state from the data page. An index storage(120) stores the index information. A programming unit(140) stores the data page and the index information. The detector reads out the data page stored in the data storage. The second count generates the verification information by counting the number of each reference threshold voltage state from the read data page. An error determining unit determines the error of the read data page based on the verification information and the index information.
Abstract translation: 提供一种用于对存储器进行编程的装置和方法，以便在验证存储在存储单元中的数据的错误时，通过使用新的多级编程方法来最小化区域开销。 数据存储（110）存储数据页。 第一计数器（130）通过从数据页计数具有至少一个参考阈值电压状态的单元的数量来生成索引信息。 索引存储（120）存储索引信息。 编程单元（140）存储数据页和索引信息。 检测器读出存储在数据存储器中的数据页。 第二计数通过从读取的数据页计数每个参考阈值电压状态的数量来生成验证信息。 错误确定单元基于验证信息和索引信息确定读取数据页的错误。
-
公开(公告)号：KR1020090061303A
公开(公告)日：2009-06-16
申请号：KR1020070128272
申请日：2007-12-11
Applicant: 삼성전자주식회사
IPC: H01L31/10 , H01L27/146
CPC classification number: H01L27/14621 , H01L27/14627 , H01L31/02165
Abstract: A photo diode and a CMOS image sensor including the same are provided to increase an amount of a sensing light by including a p-n junction photo diode including a pattern layer of metal material and a micro lens formed on a top part of the metal pattern layer. A pattern layer(13) of metal material is formed on a top part. The pattern layer of the metal material is a metal thin film layer including a contact hole pattern. The metal material is made of at least one selected among groups composed of gold, silver, copper, aluminum, and tungsten. A micro lens is formed on a top part of the pattern layer of the metal material. A dielectric film(15) is formed between the metal pattern layer and the photo diode(12). The dielectric film is made of at least one material selected among groups composed of SiO2, SiON, HfO2, and Si3N4. Thickness of the dielectric film is 3~100nm.
Abstract translation: 提供包括该光电二极管和CMOS图像传感器的光电二极管和CMOS图像传感器，以通过包括形成在金属图案层的顶部上的包括金属材料的图案层和微透镜的p-n结光电二极管来增加感测光的量。 金属材料的图案层（13）形成在顶部上。 金属材料的图案层是包括接触孔图案的金属薄膜层。 金属材料由金，银，铜，铝和钨组成的组中的至少一种制成。 微透镜形成在金属材料的图案层的顶部上。 在金属图案层和光电二极管（12）之间形成介电膜（15）。 电介质膜由选自由SiO 2，SiON，HfO 2和Si 3 N 4组成的组中的至少一种材料制成。 电介质膜的厚度为3〜100nm。
-
Patent Agency Ranking
公开(公告)号：KR1020090048877A
公开(公告)日：2009-05-15
申请号：KR1020070114958
申请日：2007-11-12
Applicant: 삼성전자주식회사
IPC: G11C16/00
CPC classification number: G11C16/10 , G11C2213/71
Abstract: 고집적화된 3차원 적층 구조의 비휘발성 메모리 소자 및 그 신뢰성 있는 동작 방법이 제공된다. 비휘발성 메모리 소자는 적층된 복수의 반도체층들을 포함한다. 복수의 낸드 스트링들은 상기 복수의 반도체층들 상에 각각 형성되고, 낸드-구조로 배치된 복수의 메모리셀들 및 하나 이상의 스트링 선택 트랜지스터를 각각 포함한다. 공통 비트 라인은 상기 복수의 메모리셀들 일측의 상기 복수의 낸드 스트링들에 공유로 연결된다. 공통 소오스 라인은 상기 복수의 메모리셀들 타측의 상기 복수의 낸드 스트링들에 공유로 연결된다. 복수의 스트링 선택 라인은 상기 공통 비트 라인으로 인가된 신호가 상기 복수의 낸드 스트링들에 선택적으로 인가되도록 상기 복수의 낸드 스트링들 각각의 상기 하나 이상의 스트링 선택 트랜지스터에 각각 결합된다.
-
公开(公告)号：KR1020090037690A
公开(公告)日：2009-04-16
申请号：KR1020070103164
申请日：2007-10-12
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/115 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L27/1203 , H01L29/42328 , H01L29/42336 , H01L29/42344 , H01L29/42352 , H01L29/66825 , H01L29/66833 , H01L21/31051
Abstract: A non-volatile memory device, a method of operating the same and method of fabricating the same is provided to obtain high operation speed by using a recess structure and a trench. A semiconductor layer(105) comprises a first area(102) and a second area(104), a plurality of control gate electrodes(150) is arranged inside the semiconductor substrate. A plurality of charge storage layers(130) is interposed between the control gate electrodes and the semiconductor layer. The charge storage layers are used as a charge storage medium for data program, and a plurality of tunneling insulation layers(120) is interposed between the semiconductor layer and the charge storage layers. A tunneling insulation layers are used as a tunneling route of an electric charge, and a blocking insulating layer(140) is interposed between the charge storage layers and the control gate electrodes. A first auxiliary electrode(170a) and a second auxiliary electrode(170b) are arranged to be opposite to each other.
Abstract translation: 提供非易失性存储器件，其操作方法和制造方法，以通过使用凹陷结构和沟槽来获得高操作速度。 半导体层（105）包括第一区域（102）和第二区域（104），多个控制栅电极（150）布置在半导体衬底的内部。 多个电荷存储层（130）插入在控制栅电极和半导体层之间。 电荷存储层用作数据程序的电荷存储介质，并且在半导体层和电荷存储层之间插入多个隧穿绝缘层（120）。 使用隧道绝缘层作为电荷的隧道路径，并且在电荷存储层和控制栅极之间插入阻挡绝缘层（140）。 第一辅助电极（170a）和第二辅助电极（170b）被布置成彼此相对。
-
公开(公告)号：KR1020090019195A
公开(公告)日：2009-02-25
申请号：KR1020070083447
申请日：2007-08-20
Applicant: 삼성전자주식회사
CPC classification number: G11C16/3418
Abstract: A non-volatile memory device and a reading method thereof are provided to confirm whether a memory cell as a reading target is in an erasing state or in a programming state when the size of the memory cell is small. A non-volatile memory device includes a first dummy memory cell(MC1), a second dummy memory cell(MC2), a plurality of normal memory cells, a ground selection transistor, and a string selection transistor. Data are not written in the first and second dummy memory cells. The normal memory cells are serially connected between the first and second dummy memory cells. The ground selection transistor is connected to the first dummy cell. The string selection transistor is connected to the second dummy cell.
Abstract translation: 提供一种非易失性存储器件及其读取方法，用于当存储单元的尺寸小时，确认作为读取对象的存储器单元是否处于擦除状态或编程状态。 非易失性存储器件包括第一虚拟存储器单元（MC1），第二虚拟存储单元（MC2），多个正常存储器单元，接地选择晶体管和串选择晶体管。 数据不写入第一和第二虚拟存储单元。 正常存储单元串联连接在第一和第二虚拟存储单元之间。 接地选择晶体管连接到第一虚拟单元。 串选择晶体管连接到第二虚拟单元。
-
公开(公告)号：KR1020090007119A
公开(公告)日：2009-01-16
申请号：KR1020070070771
申请日：2007-07-13
Applicant: 삼성전자주식회사
CPC classification number: G11C16/34 , G11C16/3459 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/30
Abstract: An operation method of nonvolatile memory device is provided to rapidly stabilize data recorded in a memory cell by inducing a boosting voltage to a channel of the memory cell. Data is recorded by supplying a program voltage to a memory cell selected among a plurality of memory cells(S110). The recorded data is stabilized(S120). Injection quantity of electron is determined by measuring a current flowed in the memory cell. Data recording quantity is verified according to the decision result. The stabilized data is verified(S130). A program completion is determined(S140). A program voltage is increased in case a program is not completed(S150). A total process is repeated by using an increased program voltage.
Abstract translation: 提供一种非易失性存储器件的操作方法，用于通过对存储单元的通道进行升压来快速稳定记录在存储单元中的数据。 通过向在多个存储单元中选择的存储单元提供编程电压来记录数据（S110）。 记录数据稳定（S120）。 通过测量在存储单元中流动的电流来确定电子的注入量。 根据决策结果验证数据记录数量。 验证稳定的数据（S130）。 确定程序完成（S140）。 在程序未完成的情况下增加程序电压（S150）。 通过使用增加的编程电压重复整个过程。
-
公开(公告)号：KR1020080101279A
公开(公告)日：2008-11-21
申请号：KR1020070047831
申请日：2007-05-16
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C2211/5642
Abstract: A memory cell write/read method and page buffer is provided to use respective optimized code at writing operation and read operation by using the different code in the writing operation and read operation. In a writing / read method of the memory cell having a plurality of threshold voltage distributions, n-bit data is written in the memory cell by using a writing code indicating corresponding threshold voltage distribution among a plurality of threshold voltage distributions. N-bit data is read from the memory cell by using a reading code indicating corresponding threshold voltage distribution among a plurality of threshold voltage distributions.
Abstract translation: 提供存储单元写入/读取方法和页面缓冲器，以便在写入操作和读取操作中通过使用不同的代码在写入操作和读取操作时使用相应的优化代码。 在具有多个阈值电压分布的存储单元的写入/读取方法中，通过使用表示多个阈值电压分布中的相应的阈值电压分布的写入代码将n位数据写入存储单元。 通过使用指示多个阈值电压分布中相应的阈值电压分布的读取代码从存储单元读取N位数据。
-
-
-
-
-
-
-
-
-
Search Results
261
records
(took 0.032 seconds)
