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    Silicon processing method and silicon substrate with etching mask
    136.
    发明公开
    Silicon processing method and silicon substrate with etching mask 审中-公开
    Siliziumverarbeitungsverfahren und Siliziumsubstrat mitÄtzmaske

    公开(公告)号：EP2159191A2

    公开(公告)日：2010-03-03

    申请号：EP09168828.3

    申请日：2009-08-27

    Applicant: Canon Kabushiki Kaisha

    Inventor： Kato, Takahisa ,  Shimada, Yasuhiro

    IPC: B81C1/00

    CPC classification number: B81C1/00626 ,  B81B2201/0271 ,  B81C1/00404 ,  B81C2201/0133 ,  B81C2201/0198

    Abstract: A silicon processing method includes: forming a mask pattern on a principal plane of a single-crystal silicon substrate; and applying crystal anisotropic etching to the principal surface to form a structure including a (111) surface and a crystal surface equivalent thereto and having width W1 and length L1. The principal plane includes a (100) surface and a crystal surface equivalent thereto or a (110) surface and a crystal surface equivalent thereto. A determining section for determining the width W1 of the structure is formed in the mask pattern. The width of the determining section for the width W1 of the mask pattern is width W2. The width of the mask pattern other than the determining section is larger than the width W2 over a length direction of the mask pattern.

    Abstract translation: 硅处理方法包括：在单晶硅衬底的主平面上形成掩模图案; 并对主表面进行结晶各向异性蚀刻，以形成包括（111）表面和与其等效的晶体表面的结构，并且具有宽度W1和长度L1。 主平面包括（100）表面和与其等效的（110）表面和与其等效的（110）表面和晶体表面。 在掩模图案中形成用于确定结构的宽度W1的确定部分。 掩模图案的宽度W1的确定部的宽度为宽度W2。 除了确定部分之外的掩模图案的宽度大于在掩模图案的长度方向上的宽度W2。

    METHOD FOR PRODUCING COMB DRIVE DEVICES USING ETCH BUFFERS
    138.
    发明授权
    METHOD FOR PRODUCING COMB DRIVE DEVICES USING ETCH BUFFERS 有权
    工艺提供使用ÄTZPUFFERNCOMB触发装置

    公开(公告)号：EP1733468B1

    公开(公告)日：2009-03-11

    申请号：EP04815065.0

    申请日：2004-12-21

    Applicant: Honeywell International Inc.

    Inventor： RIDLEY, Jeffrey, A. ,  NEUS, James, A.

    IPC: H02N1/00 ,  B81B3/00

    CPC classification number: B81C1/00698 ,  B81B2201/0271 ,  B81B2201/033 ,  B81C2201/0132

    Abstract: Methods of fabricating comb drive devices utilizing one or more sacrificial etch-buffers are disclosed. An illustrative fabrication method may include the steps of etching a pattern onto a wafer substrate defining one or more comb drive elements and sacrificial etch-buffers, liberating and removing one or more sacrificial etch-buffers prior to wafer bonding, bonding the etched wafer substrate to an underlying support substrate, and etching away the wafer substrate. In some embodiments, the sacrificial etch-buffers are removed after bonding the wafer to the support substrate. The sacrificial etch-buffers can be provided at one or more selective regions to provide greater uniformity in etch rate during etching. A comb drive device in accordance with an illustrative embodiment can include a number of interdigitated comb fingers each having a more uniform profile along their length and/or at their ends, producing less harmonic distortion during operation.

    PIEZOELECTRIC FILTER
    139.
    发明公开
    PIEZOELECTRIC FILTER 有权
    PIEZOELEKTRISCHES过滤器

    公开(公告)号：EP1804376A4

    公开(公告)日：2008-05-14

    申请号：EP05755248

    申请日：2005-07-01

    Applicant: MURATA MANUFACTURING CO

    Inventor： KUBO RYUICHI ,  OGUCHI TAKAHIRO ,  YAMADA HAJIME

    IPC: H03H9/02 ,  H01L41/08 ,  H01L41/09 ,  H01L41/18 ,  H01L41/22 ,  H01L41/23 ,  H01L41/253 ,  H01L41/313 ,  H03H9/17 ,  H03H9/25 ,  H03H9/54 ,  H03H9/58 ,  H03H9/64

    CPC classification number: H03H9/587 ,  B81B2201/0271 ,  B81C1/00238 ,  H03H9/105 ,  H03H9/1092 ,  H03H9/564

    Abstract: A piezoelectric filter having a smaller size is provided. A piezoelectric filter (10) includes a first substrate (22) having at least one first piezoelectric resonator (25) disposed on a main surface of the first substrate (22); a second substrate (12) having at least one second piezoelectric resonator (15) disposed on a main surface of the second substrate (12); a connection pattern (20) extending around the first piezoelectric resonator (25) and the second piezoelectric resonator (15) and disposed between the first substrate (22) and the second substrate (12), the main surface of the first substrate (22) facing the main surface of the second substrate (12), the first piezoelectric resonator (25) being bonded to the second piezoelectric resonator (15) with the connection pattern (20), and the first piezoelectric resonator (25) being remote from the second piezoelectric resonator (15), and a connecting layer (24x) for bonding a pad (28x) to a pad (18x), the pad 2(8x) being disposed on the main surface of the first substrate (22) and electrically connected to the first piezoelectric resonator (25), and the pad (18x) being disposed on the main surface of the second substrate (12) and electrically connected to the second piezoelectric resonator (15).

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