公开(公告)号：US07858885B2

公开(公告)日：2010-12-28

申请号：US11867647

申请日：2007-10-04

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/427 ,  H05K1/116 ,  H05K3/108 ,  H05K3/426 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2203/0353 ,  Y10T29/49123 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The present invention provides a circuit board structure, the circuit board structure consisting of a carrier board having a first surface and an opposed second surface, the carrier board being formed with at least one through hole penetrating the first and second surfaces; a conductive pillar formed in the through hole by electroplating; and a first circuit layer and a second circuit layer respectively formed on the first and second surfaces of the carrier board, the first and second circuit layers being electrically connected to the two end portions of the conductive pillar, thereby reducing spacing between adjacent conductive pillars of the carrier board and achieving high density circuit layout.

Abstract translation: 本发明提供一种电路板结构，所述电路板结构由具有第一表面和相对的第二表面的载体板组成，所述载体板形成有穿过所述第一表面和所述第二表面的至少一个通孔; 通过电镀形成在通孔中的导电柱; 以及分别形成在所述载板的所述第一和第二表面上的第一电路层和第二电路层，所述第一和第二电路层电连接到所述导电柱的两个端部，由此减小相邻导电柱之间的间隔 承载板实现高密度电路布局。

公开(公告)号：US20100101851A1

公开(公告)日：2010-04-29

申请号：US12606538

申请日：2009-10-27

Applicant: Shigetsugu Muramatsu ,  Yasuhiko Kusama

Inventor： Shigetsugu Muramatsu ,  Yasuhiko Kusama

IPC: H05K1/02 ,  H05K3/10

CPC classification number: H05K1/116 ,  H05K3/108 ,  H05K3/421 ,  H05K3/4644 ,  H05K3/4647 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2203/0542 ,  H05K2203/0733 ,  Y10T29/49155 ,  Y10T29/49204

Abstract: A wiring substrate, includes a first wiring layer, an insulating layer formed on the first wiring layer, a via conductor filled to penetrate the insulating layer in a thickness direction and connected to a connection portion of the first wiring layer, and a second wiring layer which is formed on the insulating layer and whose connection portion is connected to the via conductor, wherein, out of the first wiring layer and the second wiring layer, the connection portion of one wiring layer is formed as a land whose diameter is larger than a diameter of the via conductor, and the connection portion of other wiring layer is formed as a landless wiring portion whose diameter is equal to or smaller than a diameter of the via conductor.

Abstract translation: 布线基板包括第一布线层，形成在第一布线层上的绝缘层，填充成在厚度方向上贯穿绝缘层并与第一布线层的连接部分连接的通孔导体，以及第二布线层 其形成在绝缘层上，其连接部分连接到通孔导体，其中，在第一布线层和第二布线层之外，一个布线层的连接部分形成为直径大于 通孔导体的直径和其他布线层的连接部分形成为直径等于或小于通路导体的直径的无地布线部分。

公开(公告)号：US20090294164A1

公开(公告)日：2009-12-03

申请号：US12219079

申请日：2008-07-15

Applicant: Han Kim ,  Je Gwang Yoo ,  Chang Sup Ryu ,  Chang Gun Oh

Inventor： Han Kim ,  Je Gwang Yoo ,  Chang Sup Ryu ,  Chang Gun Oh

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K1/116 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/025 ,  H05K3/108 ,  H05K3/427 ,  H05K2201/0394 ,  H05K2201/09545 ,  Y10T29/49165

Abstract: Disclosed herein is a printed circuit board including a landless via and a method of manufacturing the printed circuit board. The printed circuit board includes a landless via having no upper land. The via includes a circuit pattern having a line width smaller than the minimum diameter of the via. The via does not have an upper land on an end surface thereof having the minimum diameter, and thus a circuit pattern connected to the via is finely formed, resulting in the high-density circuit pattern. Thus, a compact printed circuit board having a reduced number of layers is realized.

Abstract translation: 本发明公开了一种印刷电路板，其包括无轨道通孔和制造印刷电路板的方法。 印刷电路板包括没有上部焊盘的无地通孔。 通孔包括具有小于通孔的最小直径的线宽的电路图案。 通孔在其端面上没有具有最小直径的上部焊盘，因此与通孔连接的电路图案被精细地形成，导致高密度电路图案。 因此，实现了层数减少的紧凑型印刷电路板。

公开(公告)号：US20090236137A1

公开(公告)日：2009-09-24

申请号：US12227377

申请日：2006-05-17

Applicant: Yasuo Kaneda ,  Munetoshi Irisawa ,  Yuji Toyoda ,  Toyokazu Komuro ,  Katsuya Fukase ,  Toyoaki Sakai

Inventor： Yasuo Kaneda ,  Munetoshi Irisawa ,  Yuji Toyoda ,  Toyokazu Komuro ,  Katsuya Fukase ,  Toyoaki Sakai

IPC: H05K1/11 ,  G03F7/20

CPC classification number: H05K3/426 ,  H05K1/116 ,  H05K3/002 ,  H05K3/108 ,  H05K2201/09545 ,  H05K2203/0191 ,  H05K2203/0574 ,  H05K2203/1184 ,  H05K2203/1394

Abstract: There are provided a method for forming a resist pattern for preparing a circuit board having a landless or small-land-width through-hole(s) to realize a high-density circuit board, a method for producing a circuit board, and a circuit board. A method for forming a resist pattern, comprising the steps of forming a resin layer and a mask layer on a first surface of a substrate having a through-hole(s), and removing the resin layer on the through-hole(s) and on a periphery of the through-hole(s) on the first surface by supplying a resin layer removing solution from a second surface opposite to the first surface of the substrate, and a method for producing a circuit board using the method for forming a resist pattern, and a circuit board.

Abstract translation: 提供了一种形成抗蚀剂图案的方法，该抗蚀剂图案用于制备具有无轨或小地平面宽度的通孔的电路板，以实现高密度电路板，生产电路板的方法和电路 板。 一种形成抗蚀剂图案的方法，包括以下步骤：在具有通孔的基板的第一表面上形成树脂层和掩模层，并且除去通孔上的树脂层和 通过从与基板的第一表面相对的第二表面提供树脂层去除溶液，在第一表面的通孔的周边上，以及使用该抗蚀剂形成方法制造电路板的方法 图案和电路板。

公开(公告)号：US07485812B2

公开(公告)日：2009-02-03

申请号：US10987480

申请日：2004-11-11

Applicant: Kevin C. Olson ,  Alan E. Wang ,  Peter Elenius ,  Thomas W. Goodman

Inventor： Kevin C. Olson ,  Alan E. Wang ,  Peter Elenius ,  Thomas W. Goodman

IPC: H05K1/03

CPC classification number: H05K3/002 ,  H05K1/056 ,  H05K3/0052 ,  H05K3/403 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0397 ,  H05K2201/0909 ,  H05K2201/09181 ,  H05K2201/0919 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/09645 ,  H05K2201/09827 ,  H05K2203/1105 ,  H05K2203/135

Abstract: A circuit board or each circuit board of a multi-layer circuit board includes an electrically conductive sheet coated with an insulating top layer covering one surface of the conductive sheet, an insulating bottom layer covering another surface of the conductive sheet and an insulating edge layer covering an edge of the conductive sheet. An insulating interlayer can be sandwiched between a pair of adjacent circuit boards of a multi-layer circuit board assembly. A landless through-hole or via can extend through one or more of the circuit boards for connecting electrical conductors on opposing surfaces thereof.

Abstract translation: 多层电路板的电路板或每个电路板包括涂覆有覆盖导电片的一个表面的绝缘顶层的导电片，覆盖导电片另一表面的绝缘底层和覆盖 导电片的边缘。 绝缘中间层可以夹在多层电路板组件的一对相邻电路板之间。 无地通孔或通孔可以延伸通过一个或多个电路板，用于连接其相对表面上的电导体。

公开(公告)号：US20080158841A1

公开(公告)日：2008-07-03

申请号：US12034504

申请日：2008-02-20

Applicant: Yasushi INAGAKI ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi INAGAKI ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K7/02

CPC classification number: H05K1/115 ,  H01G2/06 ,  H01G4/12 ,  H01G4/224 ,  H01G4/228 ,  H01G4/248 ,  H01G4/40 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/181 ,  H05K1/183 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

Abstract translation: 片状电容器20设置在印刷电路板10中。 以这种方式，IC芯片90和每个片状电容器20之间的距离缩短，并且环路电感减小。 此外，芯片电容器20被容纳在具有大厚​​度的芯基板30中。 因此，印刷电路板的厚度不会变大。

公开(公告)号：US20080158838A1

公开(公告)日：2008-07-03

申请号：US12034517

申请日：2008-02-20

Applicant: Yasushi INAGAKI ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi INAGAKI ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K1/18

CPC classification number: H05K1/115 ,  H01G2/06 ,  H01G4/12 ,  H01G4/224 ,  H01G4/228 ,  H01G4/248 ,  H01G4/40 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/181 ,  H05K1/183 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

公开(公告)号：US20080094813A1

公开(公告)日：2008-04-24

申请号：US11867647

申请日：2007-10-04

Applicant: Shih-Ping HSU

Inventor： Shih-Ping HSU

IPC: H05K1/03

CPC classification number: H05K3/427 ,  H05K1/116 ,  H05K3/108 ,  H05K3/426 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2203/0353 ,  Y10T29/49123 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The present invention provides a circuit board structure, the circuit board structure consisting of a carrier board having a first surface and an opposed second surface, the carrier board being formed with at least one through hole penetrating the first and second surfaces; a conductive pillar formed in the through hole by electroplating; and a first circuit layer and a second circuit layer respectively formed on the first and second surfaces of the carrier board, the first and second circuit layers being electrically connected to the two end portions of the conductive pillar, thereby reducing spacing between adjacent conductive pillars of the carrier board and achieving high density circuit layout.

Abstract translation: 本发明提供一种电路板结构，所述电路板结构由具有第一表面和相对的第二表面的载体板组成，所述载体板形成有穿过所述第一表面和所述第二表面的至少一个通孔; 通过电镀形成在通孔中的导电柱; 以及分别形成在所述载板的所述第一和第二表面上的第一电路层和第二电路层，所述第一和第二电路层电连接到所述导电柱的两个端部，由此减小相邻导电柱之间的间隔 承载板实现高密度电路布局。

公开(公告)号：US07307852B2

公开(公告)日：2007-12-11

申请号：US11062672

申请日：2005-02-23

Applicant: Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/115 ,  H01G2/06 ,  H01G4/12 ,  H01G4/224 ,  H01G4/228 ,  H01G4/248 ,  H01G4/40 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/181 ,  H05K1/183 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

Abstract translation: 片状电容器20设置在印刷电路板10中。 以这种方式，IC芯片90和每个片状电容器20之间的距离缩短，并且环路电感减小。 此外，芯片电容器20被容纳在具有大厚​​度的芯基板30中。 因此，印刷电路板的厚度不会变大。

公开(公告)号：US07084354B2

公开(公告)日：2006-08-01

申请号：US10173329

申请日：2002-06-14

Applicant: David W. Boggs ,  Daryl A. Sato ,  John H. Dungan ,  Gary I. Paek

Inventor： David W. Boggs ,  Daryl A. Sato ,  John H. Dungan ,  Gary I. Paek

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/115 ,  H05K3/4644 ,  H05K2201/09245 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2201/09645 ,  H05K2201/09827 ,  Y10T29/49126

Abstract: An electronic assembly is disclosed. The electronic assembly includes a lower portion and a first elongate trace formed on an upper surface of the lower portion. The trace is covered by an upper portion, and an opening formed through an upper surface of the upper portion extends to the trace to expose a portion of the trace. A second elongate trace is formed on the upper portion. A portion of the second elongate trace positioned in the opening formed through the upper surface of the upper portion contacts the first elongate trace through the opening to form an electrical interconnection between the first trace and the second trace.