公开(公告)号：US07976714B2

公开(公告)日：2011-07-12

申请号：US11969505

申请日：2008-01-04

Applicant: Lianzhong Yu

Inventor： Lianzhong Yu

IPC: C23F1/00

CPC classification number: B81C1/00182 ,  B81B2201/0235 ,  B81C2201/0136

Abstract: Methods for producing a MEMS device from a single silicon-on-insulator (SOI) wafer. An SOI wafer includes a silicon (Si) handle layer, a Si mechanism layer and an insulator layer located between the Si handle and Si mechanism layers. An example method includes etching active components from the Si mechanism layer. Then, the exposed surfaces of the Si mechanism layer is doped with boron. Next, portions of the insulator layer proximate to the etched active components of the Si mechanism layer are removed and the Si handle layer is etched proximate to the etched active components.

Abstract translation: 从单个绝缘体上硅（SOI）晶片制造MEMS器件的方法。 SOI晶片包括硅（Si）手柄层，Si机构层和位于Si手柄和Si机构层之间的绝缘体层。 示例性方法包括从Si机理层蚀刻活性组分。 然后，Si机理层的暴露表面掺杂有硼。 接下来，去除邻近Si机理层的蚀刻的有源部件的绝缘体层的部分，并且蚀刻附近的Si处理层。

公开(公告)号：US07794610B2

公开(公告)日：2010-09-14

申请号：US10583719

申请日：2004-12-23

Applicant: Claire Divoux ,  Marie-Helene Vaudaine ,  Thierry Enot

Inventor： Claire Divoux ,  Marie-Helene Vaudaine ,  Thierry Enot

IPC: H01L21/302 ,  B81C1/00 ,  B81C3/00

CPC classification number: G02B26/085 ,  B81B2201/038 ,  B81B2201/047 ,  B81B2203/0127 ,  B81B2203/0361 ,  B81C1/00626 ,  B81C2201/0136 ,  G02B26/0833 ,  G02B26/0841 ,  Y10S29/016 ,  Y10S438/924 ,  Y10T29/42

Abstract: The invention relates to a method for making an actuation system for an optical component comprising: etching of a first face of a component, to form pads on it, etching of a second face of the component, to expose a membrane made of the same material as the pads, production of the actuation means of the pads and the membrane.

Abstract translation: 本发明涉及一种用于制造光学部件的致动系统的方法，包括：蚀刻部件的第一面，在其上形成焊盘，蚀刻部件的第二面，暴露由相同材料制成的膜 作为垫，制造垫和膜的致动装置。

公开(公告)号：US20080164576A1

公开(公告)日：2008-07-10

申请号：US11958945

申请日：2007-12-18

Applicant: Giuseppe Barillaro ,  Alessandro Diligenti ,  Caterina Riva ,  Roberto Campedelli ,  Stefano Losa

Inventor： Giuseppe Barillaro ,  Alessandro Diligenti ,  Caterina Riva ,  Roberto Campedelli ,  Stefano Losa

IPC: H01L21/04 ,  H01L29/06

CPC classification number: B81C1/00539 ,  B81B2201/038 ,  B81B2201/07 ,  B81B2201/12 ,  B81B2203/0118 ,  B81B2203/019 ,  B81C1/00595 ,  B81C2201/0136 ,  B81C2203/0714 ,  H01L27/10

Abstract: A process for manufacturing an interaction system of a microelectromechanical type for a storage medium, the interaction system provided with a supporting element and an interaction element carried by the supporting element, envisages the steps of: providing a wafer of semiconductor material having a substrate with a first type of conductivity (P) and a top surface; forming a first interaction region having a second type of conductivity (N), opposite to the first type of conductivity (P), in a surface portion of the substrate in the proximity of the top surface; and carrying out an electrochemical etch of the substrate starting from the top surface, the etching being selective with respect to the second type of conductivity (N), so as to remove the surface portion of the substrate and separate the first interaction region from the substrate, thus forming the supporting element.

Abstract translation: 一种用于制造用于存储介质的微机电类型的相互作用系统的方法，具有支撑元件的相互作用系统和由支撑元件承载的相互作用元件，其设想是提供具有基板的半导体材料晶片，其具有 第一类电导率（P）和顶面; 在所述顶表面附近的所述衬底的表面部分中形成具有与所述第一类型的导电性（P）相反的第二导电类型（N）的第一相互作用区域; 并且从顶表面开始进行基板的电化学蚀刻，所述蚀刻相对于所述第二导电类型（N）是选择性的，以便移除所述基板的表面部分并将所述第一相互作用区域与所述基板分离 ，从而形成支撑元件。

公开(公告)号：US06946398B2

公开(公告)日：2005-09-20

申请号：US10651051

申请日：2003-08-29

Applicant: Shoji Okuda ,  Hiroshi Tokunaga ,  Osamu Tsuboi

Inventor： Shoji Okuda ,  Hiroshi Tokunaga ,  Osamu Tsuboi

IPC: G02B26/08 ,  B81B3/00 ,  B81C1/00 ,  H01L21/302

CPC classification number: B81C1/0019 ,  B81B2201/0271 ,  B81C2201/0136 ,  B81C2201/019

Abstract: The method for fabricating a micro machine comprises the step of burying an oxide film 54 in a first semiconductor substrate 6, the step of bonding the first semiconductor substrate to the second semiconductor substrate with an insulation film 18 therebetween, the step of forming a first mask 66 with an opening in a first region and a second region on both sides of the first region, the step of etching the first semiconductor substrate with a first mask 66 and an oxide film 54 as a mask to thereby form a spring portion 20a integral with the first semiconductor substrate between the oxide film and the insulation film to thereby form a torsion bar including the spring portion, the step of forming a second mask 74 with an opening in the first region and the second region, the step of etching the second semiconductor substrate by using the second mask 74, and the step of etching the insulation film 18 in the first region and the second region. The thickness of the torsion bar can be easily controlled. Thus, a micro machine having a torsion bar can be fabricated with high yields.

Abstract translation: 微机的制造方法包括在第一半导体基板6中埋入氧化膜54的步骤，将第一半导体基板与绝缘膜18接合在第二半导体基板上的工序，形成第一掩模 66，在第一区域的第一区域和第二区域的开口，第一区域的两侧的第二区域，用第一掩模66和氧化物膜54作为掩模蚀刻第一半导体衬底的步骤，从而形成一个一体化的弹簧部分20 其中第一半导体衬底在氧化物膜和绝缘膜之间，从而形成包括弹簧部分的扭杆，在第一区域和第二区域中形成具有开口的第二掩模74的步骤， 通过使用第二掩模74的半导体衬底以及蚀刻第一区域和第二区域中的绝缘膜18的步骤。 可以容易地控制扭杆的厚度。 因此，可以以高产率制造具有扭杆的微型机器。

公开(公告)号：US20050181529A1

公开(公告)日：2005-08-18

申请号：US11011888

申请日：2004-12-13

Applicant: Hubert Benzel ,  Frank Schaefer ,  Simon Armbruster ,  Gerhard Lammel ,  Christoph Schelling ,  Joerg Brasas

Inventor： Hubert Benzel ,  Frank Schaefer ,  Simon Armbruster ,  Gerhard Lammel ,  Christoph Schelling ,  Joerg Brasas

IPC: B81B3/00 ,  H01L21/00 ,  H01L29/24 ,  H01L33/00

CPC classification number: B81C1/00158 ,  B81B3/007 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0116 ,  B81C2201/0136

Abstract: A manufacturing method for a micromechanical semiconductor element includes providing on a semiconductor substrate a patterned stabilizing element having at least one opening. The opening is arranged such that it allows access to a first region in the semiconductor substrate, the first region having a first doping. Furthermore, a selective removal of at least a portion of the semiconductor material having the first doping out of the first region of the semiconductor substrate is provided. In addition, a membrane is produced above the first region using a first epitaxy layer applied on the stabilizing element. In a further method step, at least a portion of the first region is used to produce a cavity underneath the stabilizing element. In this manner, the present invention provides for the production of the patterned stabilizing element by means of a second epitaxy layer, which is applied on the semiconductor substrate.

Abstract translation: 微机电半导体元件的制造方法包括在半导体衬底上提供具有至少一个开口的图案化稳定元件。 开口被布置成使得其允许接近半导体衬底中的第一区域，第一区域具有第一掺杂。 此外，提供了选择性地去除半导体衬底的第一区域中具有第一掺杂的半导体材料的至少一部分。 此外，使用施加在稳定元件上的第一外延层，在第一区域上方产生膜。 在另一方法步骤中，第一区域的至少一部分用于在稳定元件下方产生空腔。 以这种方式，本发明提供了通过施加在半导体衬底上的第二外延层来生产图案化的稳定元件。

公开(公告)号：US20050098855A1

公开(公告)日：2005-05-12

申请号：US10426015

申请日：2003-04-30

Applicant: Noriyuki Shimoji ,  Masaki Takaoka

Inventor： Noriyuki Shimoji ,  Masaki Takaoka

IPC: B81B1/00 ,  F04B43/04 ,  H01L29/06 ,  H01L29/40

CPC classification number: F04B43/043 ,  B81B2203/0353 ,  B81C1/00626 ,  B81C2201/0136 ,  H01L29/0657

Abstract: A semiconductor device and a method of producing the same is disclosed, in which a through hole is formed in the upper surface of a semiconductor substrate from the lower surface thereof, and an opening of a desired size is formed in a desired position on the upper surface of the substrate. A guide that functions as an etching stopper is formed in the semiconductor substrate. An opening having a width W2 is formed in the guide. The opening faces an opening in a mask used in the formation of a through hole, and the width W2 thereof is narrower than a width W4 of the opening in the mask. The direction in which etching progresses is controlled by the opening formed in the guide as etching is conducted from a lower surface of the substrate to an upper surface of the substrate, and thus deviations in the width W1 and position of an opening in the upper surface of the substrate can be controlled.

Abstract translation: 公开了一种半导体器件及其制造方法，其中从半导体衬底的下表面形成在半导体衬底的上表面中的通孔，并且在上部的所需位置形成所需尺寸的开口 基板的表面。 在半导体衬底中形成用作蚀刻阻挡层的引导件。 在导向件中形成宽度为W 2的开口。 开口面向形成通孔所使用的掩模中的开口，其宽度W 2比掩模中的开口的宽度W 4窄。 蚀刻进行的方向由作为蚀刻形成在导向器中的开口控制，从基板的下表面传导到基板的上表面，因此宽度W 1和上部开口的位置的偏差 可以控制基板的表面。

公开(公告)号：US20020110948A1

公开(公告)日：2002-08-15

申请号：US10011350

申请日：2001-11-12

Applicant: INTPAX, Inc.

Inventor： Liji Huang ,  Naiqian Han ,  Yahong Yao ,  Gaofeng Wang

IPC: H01L027/15 ,  H01L031/12 ,  H01L033/00 ,  H01L021/265 ,  H01L021/00

CPC classification number: B81C1/00047 ,  B81B2201/047 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C1/00571 ,  B81C2201/0109 ,  B81C2201/0136

Abstract: The present invention discloses an electro-optical device support on a substrate. The electro-optical device includes a sacrificial layer disposed on the substrate having a chamber-wall region surrounding and defining an optical chamber. The electro-optical device further includes a membrane layer disposed on top of the sacrificial layer having a chamber-removal opening surrounding and defining an electric tunable membrane for transmitting an optical signal therethrough. The electrically tunable membrane disposed on top of the optical chamber surrounded by the chamber wall regions. The chamber-wall region is doped with iondopants for maintaining the chamber-wall region for removal-resistance under a chamber-forming process performed through the chamber-removal opening. In a preferred embodiment, the chamber-wall region is a doped silicon dioxide region with carbon or nitrogen. In another preferred embodiment, the chamber-wall region is a nitrogen ion-doped SiNxOy region. In another preferred embodiment, the optical chamber is an etched chamber formed by etching through the chamber removal opening for etching off an etch-enhanced region surrounded by an etch-resistant region constituting the chamber wall.

Abstract translation: 本发明公开了一种在基片上的电光装置支架。 电光装置包括设置在基板上的牺牲层，其具有围绕并限定光学室的室壁区域。 电光装置还包括设置在牺牲层顶部的膜层，其具有围绕并限定用于透射光信号的电可调膜的室去除开口。 设置在由室壁区域围绕的光学室的顶部上的电可调膜。 在室壁区域掺杂有离子掺杂剂，用于在通过室去除开口进行的室形成过程中保持室壁区域用于去除电阻。 在优选实施例中，室壁区域是具有碳或氮的掺杂二氧化硅区域。 在另一个优选的实施方案中，室壁区域是氮离子掺杂的SiN x O y区域。 在另一个优选实施例中，光学室是通过蚀刻通过室去除开口形成的蚀刻室，用于蚀刻由构成室壁的耐蚀刻区域围绕的蚀刻增强区域。

公开(公告)号：US06379990B1

公开(公告)日：2002-04-30

申请号：US09348160

申请日：1999-07-06

Applicant: Karlheinz Müller ,  Stefan Kolb

Inventor： Karlheinz Müller ,  Stefan Kolb

IPC: H01L2100

CPC classification number: B81C1/00158 ,  B81B2201/0235 ,  B81B2203/0315 ,  B81C2201/0136 ,  B81C2203/0136 ,  G01P15/0802

Abstract: A membrane of the micromechanical semiconductor configuration is formed within a cavity. The membrane is formed by a crystalline layer within the substrate or within an epitaxial sequence of layers of the semiconductor configuration arranged on a substrate. The membrane is laid at the edge region on a support and is covered over by a covering layer supported on a counter-support. The support and the counter-support have a different etch rate from the membrane. Wet-chemical etching of the layer sequence with an etchant that is selective to the material of the membrane thus leads to the formation of a cavity around the membrane. Preferably, the layers are formed of differently doped materials.

Abstract translation: 微机械半导体结构的膜形成在空腔内。 膜由衬底内的结晶层或布置在衬底上的半导体结构的外延层序列形成。 膜被放置在支撑件上的边缘区域，并被支撑在反向支撑件上的覆盖层覆盖。 支撑体和反向支撑件具有与膜不同的蚀刻速率。 因此，使用对膜材料有选择性的蚀刻剂对层序进行湿化学蚀刻从而导致在膜周围形成空腔。 优选地，这些层由不同掺杂的材料形成。

公开(公告)号：US20020016095A1

公开(公告)日：2002-02-07

申请号：US09917572

申请日：2001-07-27

Applicant: Xerox Corporation

Inventor： David K. Fork ,  Jackson Ho ,  Rachel King-Ha Lau ,  JengPing Lu

IPC: H05K001/00 ,  H01R012/00

CPC classification number: G01R1/06716 ,  B81B2203/0118 ,  B81C1/00484 ,  B81C2201/0136 ,  B81C2203/058 ,  G01R1/06727 ,  G01R1/07342 ,  G01R3/00 ,  H01L23/49811 ,  H01L2924/0002 ,  H01R4/48 ,  H01R12/57 ,  H05K3/4092 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/4914 ,  H01L2924/00

Abstract: Efficient methods for lithographically fabricating spring structures onto a substrate containing contact pads or metal vias by forming both the spring metal and release material layers using a single mask. Specifically, a pad of release material is self-aligned to the spring metal finger using a photoresist mask or a plated metal pattern, or using lift-off processing techniques. A release mask is then used to release the spring metal finger while retaining a portion of the release material that secures the anchor portion of the spring metal finger to the substrate. When the release material is electrically conductive (e.g., titanium), this release material portion is positioned directly over the contact pad or metal via, and acts as a conduit to the spring metal finger in the completed spring structure. When the release material is non-conductive, a metal strap is formed to connect the spring metal finger to the contact pad/via.

Abstract translation: 通过使用单个掩模通过形成弹簧金属和释放材料层来将含有接触垫或金属通孔的弹性结构光刻制造到衬底上的有效方法。 具体地说，使用光致抗蚀剂掩模或电镀金属图案或使用剥离处理技术，释放材料垫与弹簧金属手指自对准。 然后使用释放掩模释放弹簧金属指，同时保持将弹簧金属指的锚固部分固定到基底的释放材料的一部分。 当释放材料是导电的（例如钛）时，该释放材料部分直接位于接触垫或金属通孔上方，并且用作在完成的弹簧结构中的弹簧金属指的导管。 当释放材料不导电时，形成金属带以将弹簧金属手指连接到接触垫/通孔。

公开(公告)号：US20010015106A1

公开(公告)日：2001-08-23

申请号：US09781798

申请日：2001-02-12

Inventor： Robert Aigner ,  Hans-Jorg Timme ,  Thomas Bever

IPC: G01L001/00 ,  G01B007/16

CPC classification number: B81C1/00801 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2207/015 ,  B81C2201/0136 ,  H04R19/005 ,  H04R19/04 ,  H04R31/00

Abstract: The invention relates to a micromechanical sensor and to a corresponding production method that includes the following steps: a) preparing a doped semiconductor wafer ; b) applying an epitaxial layer that is doped in such a way that a jump in the charge carrier density in the interface between the semiconductor wafer and the epitaxial layer occurs; c) optionally etching ventilation holes traversing the epitaxial layer and optionally filling the ventilation holes with a sacrificial material; d) depositing at least one sacrificial layer, at least one spacing layer, a membrane and optionally a semiconductor circuit on the top side of the epitaxial layer using a technology known per se, wherein the semiconductor circuit may be applied after the membrane is formed or while depositing the layers required to form the membrane; e) etching a hole on the back part of the sensor, wherein the etching method is selected in such a way that etching advances in the direction of the top side and ceases in the interference between the wafer and the epitaxial layer by changing charge carrier concentration. The invention also relates to the utilization of the micromechanical sensor in pressure sensors or microphones.

Abstract translation: 本发明涉及一种微机械传感器及相应的生产方法，包括以下步骤：a）制备掺杂半导体晶片; b）施加掺杂的外延层，使得发生半导体晶片和外延层之间的界面中的电荷载流子密度的跳跃; c）可选地蚀刻穿过外延层的通气孔，并且可选地用牺牲材料填充通风孔; d）使用本身已知的技术在外延层的顶侧上沉积至少一个牺牲层，至少一个间隔层，膜和任选的半导体电路，其中半导体电路可以在膜被形成之后施加 同时沉积形成膜所需的层; e）蚀刻传感器后部的孔，其中蚀刻方法被选择为使得蚀刻沿着顶侧的方向前进并且通过改变电荷载流子浓度而在晶片和外延层之间的干涉中停止 。 本发明还涉及在压力传感器或麦克风中利用微机械传感器。