公开(公告)号：JP2011029236A

公开(公告)日：2011-02-10

申请号：JP2009170469

申请日：2009-07-21

Applicant: Shinko Electric Ind Co Ltd ,  新光電気工業株式会社

Inventor： HORIUCHI MICHIO ,  TOKUTAKE YASUE ,  MATSUDA YUICHI ,  YAMAZAKI TOMOO ,  SAKAGUCHI YUTA

IPC: H01L23/12 ,  H05K3/46

CPC classification number: H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0227 ,  H05K1/162 ,  H05K3/4605 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09345 ,  H05K2201/09609

Abstract: PROBLEM TO BE SOLVED: To provide a wiring board which incorporates a capacitor and reduces inductance between a semiconductor element and the capacitor when the semiconductor element is mounted and to provide a semiconductor device where the semiconductor element is mounted on the wiring board. SOLUTION: The wiring board includes a core substrate 13 having an insulating base material 11 comprising an inorganic dielectric and a plurality of linear conductors 12 penetrating from one face of the insulating base member to the other face, ground wiring groups 21b and 23b arranged on both faces of the core substrate and power supply wiring groups 21c and 23c installed on both faces of the core substrate. The ground wiring group and the power supply wiring group are installed via the insulating base material. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种包含电容器的布线板，并且当安装半导体元件时，降低半导体元件与电容器之间的电感，并提供将半导体元件安装在布线板上的半导体器件。 解决方案：布线板包括具有绝缘基材11的芯基板13，其包括无机电介质和从绝缘基体的一个面到另一面的多个线状导体12，接地布线组21b和23b 配置在芯基板的两面和安装在芯基板的两面上的电源配线组21c，23c。 接地配线组和电源配线组通过绝缘基材安装。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP3877132B2

公开(公告)日：2007-02-07

申请号：JP2000353497

申请日：2000-11-20

Applicant: 富士通株式会社

Inventor： 吉志 木村 ,  宗知 森岡 ,  義彦 池元 ,  敦 菊池 ,  真紀 飯島

IPC: H05K3/46 ,  H01L23/12 ,  H01L23/13 ,  H01L23/498 ,  H05K1/02

CPC classification number: H05K1/0245 ,  H01L23/13 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K2201/09336 ,  H05K2201/09345 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2924/00

公开(公告)号：JP3732927B2

公开(公告)日：2006-01-11

申请号：JP20555097

申请日：1997-07-31

Applicant: 京セラ株式会社

Inventor： 成夫 棚橋

IPC: H05K3/46 ,  H01L23/50 ,  H01L23/538 ,  H01L23/66 ,  H05K1/00 ,  H05K1/02

CPC classification number: H05K1/0253 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0289 ,  H05K3/4644 ,  H05K2201/09345 ,  H05K2201/09672 ,  H01L2924/00

公开(公告)号：US20240074034A1

公开(公告)日：2024-02-29

申请号：US18261250

申请日：2021-11-29

Applicant: HITACHI ASTEMO, LTD.

Inventor： Akira ISHII ,  Tomio SAKASHITA

IPC: H05K1/02 ,  H05K1/14

CPC classification number: H05K1/0218 ,  H05K1/14 ,  H05K2201/09345

Abstract: An electronic control device includes a plurality of circuit boards that transmit signals to each other and a power supply connector for direct-current power. A ground line connected to a ground terminal of the power supply connector is connected to a ground of one of the plurality of circuit boards by way of a ground of another one of the plurality of circuit boards. In this way, the electronic control device including the plurality of circuit boards needs fewer noise reduction components while enabling easier routing of ground lines.

公开(公告)号：US20170132436A1

公开(公告)日：2017-05-11

申请号：US15304232

申请日：2015-04-09

Applicant: NIDEC SANKYO CORPORATION

Inventor： Kazuhiro GOMI ,  Ikuro KURIBAYASHI

IPC: G06F21/86 ,  G06K7/10 ,  G06K7/08

CPC classification number: G06F21/86 ,  G06K7/00 ,  G06K7/087 ,  G06K7/10009 ,  H05K1/0219 ,  H05K1/0275 ,  H05K2201/09345

Abstract: Provided is a printed circuit board having a breakdown detection pattern formed thereon for preventing illicit acquisition of sensitive data, the printed circuit board being configured so that false detection of a disconnection or a short in the breakdown detection pattern can be prevented. The printed circuit board (7) comprises a breakdown detection pattern layer (32) wherein a breakdown detection pattern is formed for detecting a disconnection and/or a shorting thereof, a first pattern layer (31) disposed more to a Y1 direction side than the breakdown detection pattern layer (32), a second pattern layer (33) disposed more to a Y2 direction side than the breakdown detection pattern layer (32), and signal pattern layers (34 to 36) disposed more to the Y2 direction side than the second pattern layer (33). Formed in the first pattern layer (31) are a grounding pattern and a power source pattern covering the breakdown detection pattern from the Y1 direction side. Formed in the second pattern layer (33) are a grounding pattern and a power source pattern covering the breakdown detection pattern from the Y2 direction side.

公开(公告)号：US20170118842A1

公开(公告)日：2017-04-27

申请号：US14918678

申请日：2015-10-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce J. CHAMBERLIN ,  Andreas HUBER ,  Harald HUELS ,  Thomas STRACH ,  Thomas-Michael WINKEL

IPC: H05K1/18 ,  H05K3/46 ,  H05K1/09 ,  H05K1/02 ,  H05K3/40 ,  H05K3/00 ,  H05K1/11

CPC classification number: H05K1/184 ,  B23K1/0016 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/111 ,  H05K1/113 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/185 ,  H05K1/186 ,  H05K3/0047 ,  H05K3/3447 ,  H05K3/429 ,  H05K3/46 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09345 ,  H05K2201/09381 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/10 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/1006 ,  H05K2201/10174

Abstract: Embedding a discrete electrical device in a printed circuit board (PCB) includes: providing a vertical via as a blind hole from a horizontal surface of the PCB to an electrically conductive structure in a first layer, the first layer being one layer of a first core section of a plurality of core sections vertically arranged above each other, each core section including lower and upper conductive layers, and a non-conductive layer in between; inserting the electrical device into the via, with the device extending within at least two of the core sections; establishing a first electrical connection between a first electrical device contact device and the electrically conductive structure in the first layer; and establishing a second electrical connection between a second electrical device contact and a second layer, the second layer being one of the electrically conductive layers of a second horizontal core section.

公开(公告)号：US09609742B2

公开(公告)日：2017-03-28

申请号：US14014652

申请日：2013-08-30

Applicant: SK hynix Inc.

Inventor： Eul Chul Jang ,  Qwan Ho Chung ,  Sang Joon Lim ,  Sung Woo Han

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K1/02 ,  H01L23/498 ,  H01L23/552

CPC classification number: H05K1/0224 ,  H01L23/49838 ,  H01L23/552 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K1/0253 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09681 ,  H05K2201/097 ,  H05K2201/09727 ,  H01L2924/00

Abstract: Package substrates are provided. The package substrate may include a power line and a ground line on a first surface of a substrate body; a plurality of signal lines on the first surface between the power line and the ground line; and a lower ground pattern and a lower power pattern positioned on a second surface of the substrate body opposite to the first surface. The lower ground pattern may be disposed to be opposite to the power line and the lower power pattern may be disposed to be opposite to the ground line. Related semiconductor packages are also provided.

公开(公告)号：US20160135291A1

公开(公告)日：2016-05-12

申请号：US14932944

申请日：2015-11-04

Applicant: Hsin-Ting Liu ,  Ming-Jen Lin ,  Chun-Hung Chen

Inventor： Hsin-Ting Liu ,  Ming-Jen Lin ,  Chun-Hung Chen

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/117 ,  H05K1/0253 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/094

Abstract: A printed circuit board structure includes a main body and a connecting interface. The connecting interface connects and is located at a side of the main body. The connecting interface includes conductive layers and insulation layers. The conductive layers at least include a first, a second, a third, a fourth conductive layer. The insulation layers at least include a first, a second, a third insulation layers. The insulation layers and the conductive layers are alternately disposed. The first insulation layer is located between the first conductive layer and the second conductive layer. The first conductive layer and the second conductive layer are partially overlapped in their orthographic projections on the first insulation layer. The second insulation layer is located between the second conductive layer and the third conductive layer. The third insulation layer is located between the third conductive layer and the fourth conductive layer.

Abstract translation: 印刷电路板结构包括主体和连接界面。 连接接口连接并位于主体的一侧。 连接界面包括导电层和绝缘层。 导电层至少包括第一，第二，第三，第四导电层。 绝缘层至少包括第一绝缘层，第二绝缘层，第二绝缘层。 绝缘层和导电层交替设置。 第一绝缘层位于第一导电层和第二导电层之间。 第一导电层和第二导电层在其第一绝缘层上的正投影部分重叠。 第二绝缘层位于第二导电层和第三导电层之间。 第三绝缘层位于第三导电层和第四导电层之间。

公开(公告)号：US20140175680A1

公开(公告)日：2014-06-26

申请号：US14014652

申请日：2013-08-30

Applicant: SK hynix Inc.

Inventor： Eul Chul JANG ,  Qwan Ho CHUNG ,  Sang Joon LIM ,  Sung Woo HAN

IPC: H05K1/02 ,  H01L23/528

CPC classification number: H05K1/0224 ,  H01L23/49838 ,  H01L23/552 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K1/0253 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09681 ,  H05K2201/097 ,  H05K2201/09727 ,  H01L2924/00

Abstract: Package substrates are provided. The package substrate may include a power line and a ground line on a first surface of a substrate body; a plurality of signal lines on the first surface between the power line and the ground line; and a lower ground pattern and a lower power pattern positioned on a second surface of the substrate body opposite to the first surface. The lower ground pattern may be disposed to be opposite to the power line and the lower power pattern may be disposed to be opposite to the ground line. Related semiconductor packages are also provided.

Abstract translation: 提供封装衬底。 封装基板可以包括在基板主体的第一表面上的电源线和接地线; 电源线和接地线之间的第一表面上的多条信号线; 以及位于基板主体的与第一表面相对的第二表面上的较低接地图案和较低功率图案。 下接地图案可以被布置成与电力线相对，并且下功率图案可以被设置为与接地线相对。 还提供了相关的半导体封装。

公开(公告)号：US20120241906A1

公开(公告)日：2012-09-27

申请号：US13389364

申请日：2010-08-04

Applicant: Naoya Nakanishi

Inventor： Naoya Nakanishi

IPC: H01L29/92

CPC classification number: H05K1/0231 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09345 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/10674

Abstract: An object of the present invention is to provide a capacitor-incorporated wiring substrate in which connection reliability can be improved through ensuring of a path for supply of electric potential even upon occurrence of a faulty connection in a via-conductor group. In a capacitor-incorporated wiring substrate of the present invention, a capacitor 50 is accommodated in a core 11, and a first and a second buildup layers 12 and 13 are formed on the upper and lower sides, respectively, of the capacitor 50. The capacitor-incorporated wiring substrate has a first via-conductor group to be connected to a first electric potential, and a second via-conductor group to be connected to a second electric potential. A first electrode pattern connected to the first via-conductor group, and a plurality of second electrode patterns connected to the second via-conductor group, are formed in a front-surface electrode layer 51 of the capacitor 50. A first conductor pattern connected to the first via-conductor group, and a plurality of second conductor patterns connected to the second via-conductor group, are formed in a proximate conductor layer 31 of a first buildup layer 12. Each of the second electrode patterns and each of the second conductor patterns connect a predetermined number of via electrodes and extend in such a manner as to be orthogonal to each other.

Abstract translation: 本发明的目的是提供一种通过确保即使在通孔导体组中发生故障连接而产生电位的路径也可以提高连接可靠性的电容器配线布线基板。 在本发明的电容器配线基板中，电容器50容纳在芯体11中，在电容器50的上侧和下侧分别形成有第一和第二堆积层12和13。 电容器配合的布线基板具有要连接到第一电位的第一通孔导体组和要连接到第二电位的第二通孔导体组。 连接到第一通孔导体组的第一电极图案和连接到第二通孔导体组的多个第二电极图案形成在电容器50的前表面电极层51中。第一导体图案连接到 第一通孔导体组以及连接到第二通孔导体组的多个第二导体图案形成在第一堆积层12的邻近的导体层31中。每个第二电极图案和每个第二导体 图案连接预定数量的通孔电极并以彼此正交的方式延伸。