公开(公告)号：EP1612818A1

公开(公告)日：2006-01-04

申请号：EP05009881.3

申请日：2005-05-06

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： Borland, William J. ,  Pyada, Hena ,  Ferguson, Saul

IPC: H01G4/33 ,  H01L27/00 ,  H01L21/02

CPC classification number: H05K1/162 ,  H05K3/061 ,  H05K3/429 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of embedding thick-film capacitors includes covering capacitor layers with a protective coating prior to etching to prevent etching solutions from coming in contact with and damaging the capacitor layers.

Abstract translation: 嵌入厚膜电容器的方法，包括覆盖电容器层与蚀刻，以防止与接触并损坏电容器层蚀刻溶液之前的保护涂层。

公开(公告)号：EP1570713A1

公开(公告)日：2005-09-07

申请号：EP03813475.5

申请日：2003-12-12

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： BORLAND, William, J. ,  FERGUSON, Saul ,  MCGREGOR, David, R.

IPC: H05K1/16 ,  H05K3/46

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09763

Abstract: A printed wiring board (PWB) has stacked innerlayer panels (1001, 1002, 1003, ...) comprised of passive circuit elements (105). The passive elements (105) can include capacitors with electrode terminations located within the footprints of the capacitor electrodes (170, 180). The capacitor terminations are therefore closely spaced, reducing the capacitors' contributions to loop inductance in the innerlayer. Capacitor terminations within the electrode footprints also reduce the PWB board surface area used in forming the capacitors. The capacitor terminations are connected by circuit conductors (1021, 1022).

公开(公告)号：EP1445795A2

公开(公告)日：2004-08-11

申请号：EP04001264.3

申请日：2004-01-21

Applicant: FRIWO Gerätebau GmbH

Inventor： Bothe, Michael ,  Mörbe, Stefan

IPC: H01L21/02

CPC classification number: H01L21/00 ,  H01L27/08 ,  H01L28/40 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/162 ,  H05K1/167 ,  H05K3/06 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/4061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0187 ,  H05K2201/0347 ,  H05K2201/09036 ,  H05K2201/09672 ,  H05K2201/09763 ,  H05K2203/0369 ,  H05K2203/063 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49128

Abstract: Die vorliegende Erfindung bezieht sich auf ein Verfahren zum Herstellen einer elektrischen Baugruppe mit einem Schaltungsträger und mindestens einem in dem Schaltungsträger integrierten passiven Bauelement, das ein elektrisch funktionales Material aufweist. Um ein verbessertes Verfahren zum Herstellen einer elektrischen Baugruppe mit einem Schaltungsträger und mindestens einem in dem Schaltungsträger integrierten passiven Bauelement anzugeben, das die schnelle und kostengünstige Herstellung einerseits gewährleistet und andererseits eine hohe Flexibilität bei der Wahl der beteiligten elektrisch funktionalen Materialien ermöglicht, weist das Verfahren die folgenden Schritte auf:

Strukturieren des Schaltungsträgers, wobei mindestens eine Aussparung für das passive Bauelement geschaffen wird,
Einbringen des elektrisch funktionalen Materials in einem Rohzustand in die Aussparung des Schaltungsträgers,
Umwandeln des elektrisch funktionalen Materials aus dem Rohzustand in einen Endzustand mittels Energiezufuhr.

Abstract translation: 本发明涉及一种用于制造一种电气组件，其包括一个电路载体和包括电功能性材料在无源设备的至少一个集成电路的载体的方法。 为了提供用于制造电气组件，其包括一个电路载体和至少一个集成在电路载体无源部件，一方面保证了快速和廉价的制造，并在另一方面，允许参与电功能材料的选择高灵活性提供一种改进的方法，该方法包括 下列步骤：构造所述电路的载体，其中，用于所述无源部件的至少一个凹部被提供，引入在原始状态下的电功能材料进入电路载体的凹部中，通过能量输入装置从原始状态转换的电功能材料成最终状态。

公开(公告)号：EP1265466A3

公开(公告)日：2004-07-21

申请号：EP02253836.7

申请日：2002-05-31

Applicant: Dai Nippon Printing Co., Ltd. ,  D.T. Circuit Technology Co. Ltd.

Inventor： Fukuoka, Yoshitaka, D.T. Circuit Technology Co Ltd ,  Serizawa, Tooru, c/o Dai Nippon Printing Co., Ltd ,  Yagi, Hiroshi, c/o Dai Nippon Printing Co., Ltd ,  Shimada, Osamu, c/o D.T. Circuit Techn. Co., Ltd. ,  Harai, Hiroyuki, c/o D.T. Circuit Techn. Co., Ltd. ,  Yamaguchi, Yuji, c/o Dai Nippon Printing Co., Ltd

IPC: H05K3/46 ,  H05K1/16

CPC classification number: H05K1/162 ,  H05K1/095 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09763 ,  H05K2203/0338 ,  H05K2203/1189 ,  Y10T29/4902 ,  Y10T29/49099 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: A fabricating method of a wiring board (7) provided with passive elements is disclosed. The fabricating method includes coating one or both of resistive paste (3) and dielectric paste (2) on at least any one of first surfaces of a first metal foil and a second metal foil (1) each of which has a first surface and a second surface; arranging an insulating board (5) having thermo-plasticity and thermo-setting properties so as to face the first surface of the coated first metal foil (4), and arranging the first surface side of the coated second metal foil (4) so as to face a surface different from a surface to which the coated first metal foil (4) faces of the insulating board (5); forming a double-sided wiring board (6) by stacking, pressurizing and heating the arranged coated first metal foil (4), insulating board (5), and coated second metal foil (4), and thereby integrating these; and patterning the first metal foil and/or the second metal foil (1).

公开(公告)号：EP1154481A3

公开(公告)日：2003-01-29

申请号：EP01304079.5

申请日：2001-05-04

Applicant: SHINKO ELECTRIC INDUSTRIES CO. LTD.

Inventor： Mashino, Naohiro

IPC: H01L23/498 ,  H01L23/538 ,  H05K1/16 ,  H01L23/64

CPC classification number: H01L23/642 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15788 ,  H05K1/141 ,  H05K1/162 ,  H05K3/42 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/10734 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: An interposer (30) is adapted to be used between a mounting board (36) and a semiconductor chip (50) which is to be mounted on the mounting board (36). The interposer (30) comprises: a heat-resistant insulator (10) having first and second surfaces, the insulator (10) being provided with a plurality of through-holes (12) opened at the first and second surfaces; wiring patterns (18) formed on the first and second surfaces of the insulator electrically connected to each other by means of a conductor (14) provided on an inner wall of at least one of the through-holes (12); and a capacitor (28). The capacitor (28) comprises first electrode (18) formed on the insulator (10) and having a connecting portion (14) formed on an inner wall of at least one of the other through-holes (12), a dielectric layer (20) formed on the first electrode (18) and a second electrode (24) formed on the dielectric layer (20).

公开(公告)号：EP0899992A2

公开(公告)日：1999-03-03

申请号：EP98306562.4

申请日：1998-08-18

Applicant: LUCENT TECHNOLOGIES INC.

Inventor： Kola, Ratnaji Rao ,  Watts, Roderick Kent ,  Manzione, Louis Thomas

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/429 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2203/0315 ,  Y10T29/435 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: The specification describes of multilevel printed circuit boards and a process for their manufacture in which capacitors and other passive components are buried between levels of the multilevel board. The capacitor in the multilevel structure is designed so that access is conveniently provided to connect from the parallel plate electrodes of the interlevel capacitor to the board surface or to another board level using plated through hole interconnects.

Abstract translation: 多层印刷电路板的说明书描述和他们在哪电容器和其它无源元件的制造过程被埋入多级电路板之间的水平。 在所述多级结构中的电容器被设计成没有访问被方便地提供以从级间电容板表面或另一板级的平行平板电极连接用通孔互连电镀。

公开(公告)号：EP0719079A1

公开(公告)日：1996-06-26

申请号：EP95119116.2

申请日：1995-12-05

Applicant: KANTO KASEI CO., LTD.

Inventor： Tsuchida, Akihito ,  Sekino, Yoshito

IPC: H05K1/16

CPC classification number: H05K1/167 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/09563 ,  H05K2201/09763

Abstract: A resistor (5) is provided in a conductor layer (4) by being electrically connected thereto so that a surface of the resistor (5) and that of the conductor layer (4) is included in one plane in the direction of the thickness of a printed board (2) with the conductor layer (4) provided in a base (2') for a printed circuit.

Abstract translation: 通过电连接到导体层（4）中，电阻器（5）被设置在导体层（4）中，使得电阻器（5）的表面和导体层（4）的表面被包括在厚度方向上的一个平面中 印刷电路板（2），其中导体层（4）设置在用于印刷电路的基座（2'）中。

公开(公告)号：EP1445795B1

公开(公告)日：2011-04-27

申请号：EP04001264.3

申请日：2004-01-21

Applicant: FRIWO Gerätebau GmbH

Inventor： Bothe, Michael ,  Mörbe, Stefan

IPC: H05K1/16 ,  H01L21/02

CPC classification number: H01L21/00 ,  H01L27/08 ,  H01L28/40 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/162 ,  H05K1/167 ,  H05K3/06 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/4061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0187 ,  H05K2201/0347 ,  H05K2201/09036 ,  H05K2201/09672 ,  H05K2201/09763 ,  H05K2203/0369 ,  H05K2203/063 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49128

公开(公告)号：EP1777714B1

公开(公告)日：2010-07-07

申请号：EP06019851.2

申请日：2006-09-22

Applicant: Georgia Tech Research Corporation

Inventor： Wan, Lixi

IPC: H01G4/228 ,  H05K1/00 ,  H01L21/00

CPC classification number: H05K1/162 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09618 ,  H05K2201/09763 ,  Y10S257/908

公开(公告)号：EP1777744A3

公开(公告)日：2010-05-12

申请号：EP06019852.0

申请日：2006-09-22

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： Swaminathan, Madhavan ,  Wan, Lixi ,  Engin, Ege ,  Muthana, Prathap

IPC: H01L23/498 ,  H05K1/16 ,  H01L23/50 ,  H01L23/64

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09763 ,  Y10S257/904 ,  Y10S257/924 ,  H01L2924/00

Abstract: One embodiment of the present invention provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz comprising installing in said package an array of embedded discrete ceramic capacitors (1600), and optionally planar capacitor layers (1500). A further embodiment provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz comprising using an array of embedded discrete ceramic capacitors with different resonance frequencies, arranged in such a way that the capacitor array's impedance vs frequency curve in the critical mid-frequency range yields impedance values at or below a targeted impedance value.