公开(公告)号：US20230365396A1

公开(公告)日：2023-11-16

申请号：US18142373

申请日：2023-05-02

Applicant: TDK CORPORATION

Inventor： Toyotaka KOBAYASHI

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0021 ,  B81C1/00158 ,  B81B2201/0257 ,  B81B2203/0315 ,  B81B2203/0353 ,  B81B2207/015 ,  B81C2201/0154 ,  B81C2201/0159

Abstract: Disclosed herein is a MEMS sensor package that includes a substrate, an annular-shaped first dry film pattern stuck to one surface of the substrate, and a MEMS sensor chip including a tubular support and a detection part which is supported on the support so as to overlap a cavity of the support. The MEMS sensor chip is fixed to the substrate by sticking an annular mounting surface of the support to the first dry film pattern.

公开(公告)号：US11673798B2

公开(公告)日：2023-06-13

申请号：US17084389

申请日：2020-10-29

Applicant: International Business Machines Corporation ,  THE UNIVERSITY OF BASEL

Inventor： Gabriel Fernando Puebla Hellmann ,  Diego Monserrat Lopez ,  Ute Drechsler ,  Marcel Mayor ,  Emanuel Marc Löertscher

IPC: B81C1/00 ,  B81B1/00 ,  B01L3/00

CPC classification number: B81C1/00119 ,  B01L3/502707 ,  B01L3/502715 ,  B81B1/002 ,  B01L2200/12 ,  B01L2300/12 ,  B01L2300/168 ,  B81B2201/058 ,  B81B2203/0353 ,  B81B2203/04 ,  B81C2201/0132 ,  B81C2201/0159 ,  B81C2201/0178

Abstract: A device includes a first layer of an electrically insulating material and a second layer of a non-electrically insulating material (e.g., semiconductor or electrically conductive) extending on the first layer. The second layer is structured so as to define opposite, lateral walls of a microchannel, a bottom wall of which is defined by an exposed surface of the first layer. The second layer is further structured to form one or more electrical insulation barriers; each barrier includes a line of through holes, each surrounded by an oxidized region of the material of the second layer. The through holes alternate with oxidized portions of the oxidized region along the line. Each barrier extends, as a whole, laterally across the second layer up to one of the lateral walls and delimits two sections of the second layer on each side of the barrier and on a same side of the microchannel.

公开(公告)号：US11644757B2

公开(公告)日：2023-05-09

申请号：US16721786

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Changhua Liu ,  Jianyong Mo ,  Liang Zhang

IPC: G03F7/20 ,  B81B1/00 ,  B81C1/00

CPC classification number: G03F7/70733 ,  B81B1/00 ,  B81C1/00111 ,  G03F7/201 ,  B81B2203/0361 ,  B81C2201/0159

Abstract: Embodiments disclosed herein include lithographic patterning systems for non-orthogonal patterning and devices formed with such patterning. In an embodiment, a lithographic patterning system comprises an actinic radiation source, where the actinic radiation source is configured to propagate light along an optical axis. In an embodiment, the lithographic patterning system further comprises a mask mount, where the mask mount is configurable to orient a surface of a mask at a first angle with respect to the optical axis. In an embodiment, the lithographic patterning system further comprises a lens module, and a substrate mount, where the substrate mount is configurable to orient a surface of a substrate at a second angle with respect to the optical axis.

公开(公告)号：US09828241B2

公开(公告)日：2017-11-28

申请号：US15197418

申请日：2016-06-29

Applicant: HYUNDAI MOTOR COMPANY

Inventor： Ilseon Yoo

IPC: H01L21/00 ,  B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00269 ,  B81B7/007 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/04 ,  B81C2201/013 ,  B81C2201/0159 ,  B81C2203/0118 ,  B81C2203/031 ,  B81C2203/035 ,  B81C2203/036

Abstract: A manufacturing method of a MEMS sensor includes forming a first substrate, wherein the first substrate includes a lower electrode provided at one surface thereof, forming a second substrate, wherein the second substrate includes a first concave-convex portion provided at one surface thereof, first-bonding one surface of the first substrate and one surface of the second substrate to face each other, forming a third substrate, wherein the third substrate includes an upper electrode provided at one surface thereof, second-bonding another surface of the second substrate and one surface of the third substrate to face each other, and forming an electrode line on another surface of the third substrate to be connected to the lower electrode and the upper electrode.

公开(公告)号：US20170247247A1

公开(公告)日：2017-08-31

申请号：US15053456

申请日：2016-02-25

Applicant: Freescale Semiconductor, Inc.

Inventor： Qing Zhang ,  Mohommad Choudhuri ,  Gul Zeb

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/008 ,  B81B2201/0214 ,  B81B2207/015 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/0159 ,  B81C2201/016 ,  B81C2201/019 ,  G01N27/223

Abstract: A semiconductor device composed of a capacitive humidity sensor comprised of a moisture-sensitive polymer layer electrografted to an electrically conductive metal layer situated on an CMOS substrate or a combined MEMS and CMOS substrate, and exposed within an opening through a passivation layer, packages composed of the encapsulated device, and methods of forming the capacitive humidity sensor within the semiconductor device, are provided.

公开(公告)号：US20170246611A1

公开(公告)日：2017-08-31

申请号：US15444010

申请日：2017-02-27

Applicant: SMARTTIP BV

Inventor： Edin Sarajlic

IPC: B01J19/08 ,  C01B21/068 ,  B81C1/00

CPC classification number: B81C1/0015 ,  A61B5/150022 ,  A61B5/150282 ,  A61B5/150396 ,  A61B5/150511 ,  A61B5/150519 ,  A61B5/150984 ,  A61B5/15142 ,  A61M37/0015 ,  B81B2201/057 ,  B81B2201/12 ,  B81B2203/0118 ,  B81B2203/0353 ,  B81C1/00087 ,  B81C1/00111 ,  B81C1/00119 ,  B81C2201/0132 ,  B81C2201/0143 ,  B81C2201/0159 ,  B81C2201/0198 ,  C01B21/0687

Abstract: A method of manufacturing a plurality of through-holes in a layer of first material by subjecting part of the layer of said first material to ion beam milling.For batch-wise production, the method comprises after a step of providing the layer of first material and before the step of ion beam milling, providing a second layer of a second material on the layer of first material, providing the second layer of the second material with a plurality of holes, the holes being provided at central locations of pits in the first layer, and subjecting the second layer of the second material to said step of ion beam milling at an angle using said second layer of the second material as a shadow mask.

公开(公告)号：US20170015548A1

公开(公告)日：2017-01-19

申请号：US14963362

申请日：2015-12-09

Applicant: Texas Instruments Incorporated

Inventor： Jie Mao ,  Hau Nguyen ,  Luu Nguyen ,  Anindya Poddar

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00873 ,  B81B7/007 ,  B81B2201/0214 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0278 ,  B81B2201/0292 ,  B81B2201/047 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00333 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0159 ,  B81C2201/0181 ,  B81C2201/0188 ,  B81C2203/0136 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3121 ,  H01L24/19 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/96 ,  H01L2924/3511

Abstract: A method for fabricating packaged semiconductor devices (100) with an open cavity (110a) in panel format; placing (process 201) on an adhesive carrier tape a panel-sized grid of metallic pieces having a flat pad (230) and symmetrically placed vertical pillars (231); attaching (process 202) semiconductor chips (101) with sensor systems face-down onto the tape; laminating (process 203) and thinning (process 204) low CTE insulating material (234) to fill gaps between chips and grid; turning over (process 205) assembly to remove tape; plasma-cleaning assembly front side, sputtering and patterning (process 206) uniform metal layer across assembly and optionally plating (process 209) metal layer to form rerouting traces and extended contact pads for assembly; laminating (process 212) insulating stiffener across panel; opening (process 213) cavities in stiffener to access the sensor system; and singulating (process 214) packaged devices by cutting metallic pieces.

Abstract translation: 一种以面板格式制造具有开口腔（110a）的封装半导体器件（100）的方法; 将具有平垫（230）和对称放置的垂直柱（231）的金属片的面板尺寸网格放置（处理201）在粘合剂载带上。 将具有传感器系统的半导体芯片（工艺202）面朝下地附接到带上; 层压（工艺203）和减薄（工艺204）低CTE绝缘材料（234）以填充芯片和网格之间的间隙; 翻转（过程205）组装以去除胶带; 等离子体清洁组件正面，溅射和图案化（工艺206）跨组合均匀的金属层和任选的电镀（工艺209）金属层以形成重新布线迹线和扩展的接触垫用于组装; 层压（工艺212）跨板的绝缘加强件; 在加强件中打开（过程213）空腔以接近传感器系统; 并通过切割金属片来分割（处理214）包装的装置。

公开(公告)号：US20160280537A1

公开(公告)日：2016-09-29

申请号：US15178512

申请日：2016-06-09

Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY

Inventor： Michael D. HENRY ,  Andrew P. HOMYK ,  Axel SCHERER ,  Thomas A. TOMBRELLO ,  Sameer WALAVALKAR

IPC: B81C1/00 ,  B81B1/00 ,  B01J19/00

CPC classification number: B81C1/00111 ,  B01J19/0046 ,  B01J2219/00504 ,  B01J2219/00664 ,  B81B1/006 ,  B81B2203/0361 ,  B81B2207/056 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0159 ,  G01N1/405 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3086 ,  Y10T436/25375

Abstract: Methods for fabricating of high aspect ratio probes and deforming micropillars and nanopillars are described. Use of polymers in deforming nanopillars and micropillars is also described.

公开(公告)号：US09005548B2

公开(公告)日：2015-04-14

申请号：US12712097

申请日：2010-02-24

Applicant: Michael D. Henry ,  Andrew P. Homyk ,  Axel Scherer ,  Thomas A. Tombrello ,  Sameer Walavalkar

Inventor： Michael D. Henry ,  Andrew P. Homyk ,  Axel Scherer ,  Thomas A. Tombrello ,  Sameer Walavalkar

IPC: B01L3/00 ,  H01L21/308 ,  B81C1/00 ,  H01L21/3065

CPC classification number: B81C1/00111 ,  B01J19/0046 ,  B01J2219/00504 ,  B01J2219/00664 ,  B81B1/006 ,  B81B2203/0361 ,  B81B2207/056 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0159 ,  G01N1/405 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3086 ,  Y10T436/25375

Abstract: Methods for fabricating of high aspect ratio probes and deforming micropillars and nanopillars are described. Use of polymers in deforming nanopillars and micropillars is also described.

Abstract translation: 描述了制造高纵横比探针和变形微柱和纳米柱的方法。 还描述了聚合物在变形纳米柱和微柱体中的使用。

公开(公告)号：US08246889B2

公开(公告)日：2012-08-21

申请号：US12555428

申请日：2009-09-08

Applicant: Sunghoon Kwon ,  SeungAh Lee ,  Wook Park ,  SuEun Chung

Inventor： Sunghoon Kwon ,  SeungAh Lee ,  Wook Park ,  SuEun Chung

IPC: B28B7/30

CPC classification number: G03F7/70341 ,  B29C64/106 ,  B29L2031/756 ,  B33Y30/00 ,  B81C99/0095 ,  B81C2201/0159 ,  F15B7/08 ,  F15B15/10 ,  G03B27/54 ,  G03F7/20 ,  G03F7/70416

Abstract: An optofluidic lithography system including a membrane, a microfluidic channel, and a pneumatic chamber is provided. The membrane may be positioned between a pneumatic chamber and a microfluidic channel. The microfluidic channel may have a height corresponding to a displacement of the membrane and have a fluid flowing therein, the fluid being cured by light irradiated from the bottom to form a microstructure. The pneumatic chamber may induce the displacement of the membrane depending on an internal atmospheric pressure thereof.

Abstract translation: 提供了包括膜，微流体通道和气动室的光流体光刻系统。 膜可以位于气动室和微流体通道之间。 微流体通道可以具有对应于膜的位移的高度并且具有在其中流动的流体，流体由从底部照射的光固化以形成微结构。 气动室可以根据其内部大气压力而引起膜的移位。