公开(公告)号：US20030151905A1

公开(公告)日：2003-08-14

申请号：US10073701

申请日：2002-02-11

Applicant: ADC DSL Systems, Inc.

Inventor： Gary Gottlieb

IPC: H05K007/06

CPC classification number: H05K1/116 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/0969 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A substrate having a conductive plane and a via passing through the conductive plane is provided. The conductive plane contacts the via to electrically interconnect the via and the conductive plane. A gap in the conductive plane separates a surface of the via from the conductive plane to provide an uninterrupted path for electrical current flowing substantially on the surface of the via.

Abstract translation: 提供具有导电平面和穿过导电平面的通孔的基板。 导电平面与通孔接触以使通孔和导电平面电互连。 导电平面中的间隙将通孔的表面与导电平面分开，以提供基本上在通孔表面上流动的电流的不间断路径。

公开(公告)号：US20030076197A1

公开(公告)日：2003-04-24

申请号：US10001781

申请日：2001-10-24

Inventor： Istvan Novak ,  Valerie St.Cyr ,  Michael C. Freda ,  Merle Tetreault

IPC: H01P005/12

CPC classification number: H05K1/0234 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K1/167 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10643 ,  Y02P70/611

Abstract: A method for achieving a desired value of electrical impedance between conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the conductors. The resistance elements may be annular resistors, and may provide the designer a greater degree of control of the system ESR. The annular resistors may comprise a first terminal, an annular resistor, and a second terminal. The second terminal may be located within the confines of the annular resistor. The annular resistors may be printed onto a conductive plane (e.g. a power plane or a ground plane), or may be a discrete component.

Abstract translation: 一种用于通过电耦合多个旁路电容器和在导体之间串联的对应的电阻元件来实现电力分配结构的导体之间的电阻抗的期望值的方法。 电阻元件可以是环形电阻器，并且可以向设计者提供对系统ESR的更大程度的控制。 环形电阻器可以包括第一端子，环形电阻器和第二端子。 第二端子可以位于环形电阻器的范围内。 环形电阻器可以印刷到导电平面（例如电源平面或接地平面）上，或者可以是分立的部件。

公开(公告)号：US06455783B1

公开(公告)日：2002-09-24

申请号：US09554481

申请日：2000-05-11

Applicant: Kiyotaka Tsukada ,  Mitsuhiro Kondo ,  Naoto Ishida ,  Kouji Asano ,  Hisashi Minoura

Inventor： Kiyotaka Tsukada ,  Mitsuhiro Kondo ,  Naoto Ishida ,  Kouji Asano ,  Hisashi Minoura

IPC: H05K103

CPC classification number: H05K3/403 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0082 ,  H05K3/064 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09454 ,  H05K2201/09518 ,  H05K2201/09645 ,  H05K2203/0554 ,  H05K2203/1394 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A method for manufacturing a multilayer printed circuit board that shortens the distance between pattern layers and facilitates formation of a minute conductive hole having superior conductive reliability. A core substrate (21) including ad core pattern (12, 13), which has a pad (101, 111), is first prepared. Then, a laminated plate is formed by laminating an insulating layer (22) on the surface of the core substrate. Afterward, a surface pattern (11) is formed on the surface of the laminated plate. Further, the conductive hole (30, 31) is formed by irradiating a laser beam at the laminated plate. The bottom opening of the conductive hole (30, 31) is covered by the pad (101, 111).

Abstract translation: 一种制造多层印刷电路板的方法，其缩短图案层之间的距离，并且有助于形成具有优良导电可靠性的微小导电孔。 首先准备包括具有焊盘（101,111）的焊盘图案（12,13）的芯基板（21）。 然后，通过在芯基板的表面上层叠绝缘层（22）来形成层压板。 之后，在层叠板的表面上形成表面图案（11）。 此外，通过在层压板上照射激光束来形成导电孔（30,31）。 导电孔（30,31）的底部开口由垫（101,111）覆盖。

公开(公告)号：US6010769A

公开(公告)日：2000-01-04

申请号：US875093

申请日：1997-07-16

Applicant: Kenji Sasaoka ,  Hiroshi Odaira ,  Madoka Fujiwara ,  Fumitoshi Ikegaya ,  Takahiro Mori

Inventor： Kenji Sasaoka ,  Hiroshi Odaira ,  Madoka Fujiwara ,  Fumitoshi Ikegaya ,  Takahiro Mori

IPC: H01L21/48 ,  H01L23/538 ,  H05K1/09 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  B32B3/00

CPC classification number: H01L24/16 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/17 ,  H05K1/116 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4647 ,  H05K3/4652 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K1/095 ,  H05K2201/0355 ,  H05K2201/09454 ,  H05K2201/0969 ,  H05K2201/09863 ,  H05K2203/1189 ,  H05K2203/1572 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A multilayered wiring board using conductive pillars for the interconnection of wiring layers. Since through holes are bored in the via lands of the wiring layers of the multilayered wiring board, the stress applied between the conductive pillars and wiring layers can be released at the time of connecting the conductive pillars to the via lands. Since the external side face of each conductive pillar smoothly continues to the surface of the via land at the contact section between the conductive pillar and the via land, the notch effect is relieved. Therefore, the reliability of the interconnection is secured even when a stress is applied to the connections during the manufacturing of the multilayered wiring board, and the mounting of electronic elements, etc.

Abstract translation: PCT No.PCT / JP96 / 03378 Sec。 371日期1997年7月16日 102（e）日期1997年7月16日PCT 1996年11月18日PCT公布。 第WO97 / 19579号公报 日期1997年5月29日一种使用导电柱的多层布线板用于布线层的互连。 由于通孔在多层布线板的布线层的通孔焊盘中钻孔，所以在将导电柱连接到通孔焊盘时，可以释放在导电柱和布线层之间施加的应力。 由于每个导电柱的外侧面在导电柱和通孔焊盘之间的接触部处平滑地延续到通路接合面的表面，所以能够消除切口效果。 因此，即使在制造多层布线基板期间对连接件施加应力并且安装电子元件等时也确保互连的可靠性。

公开(公告)号：US5638598A

公开(公告)日：1997-06-17

申请号：US462853

申请日：1995-06-05

Applicant: Akishi Nakaso ,  Kouichi Tsuyama ,  Akinari Kida ,  Shuichi Hatakeyama ,  Naoyuki Urasaki

Inventor： Akishi Nakaso ,  Kouichi Tsuyama ,  Akinari Kida ,  Shuichi Hatakeyama ,  Naoyuki Urasaki

IPC: H05K3/00 ,  H05K3/06 ,  H05K3/40 ,  H05K3/46 ,  H01K3/10

CPC classification number: H05K3/4069 ,  H05K3/0055 ,  H05K2201/0305 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0355 ,  H05K2201/09454 ,  H05K2201/09745 ,  H05K2203/0346 ,  H05K2203/0384 ,  H05K2203/0554 ,  H05K2203/1453 ,  H05K3/06 ,  H05K3/4038 ,  H05K3/4623 ,  H05K3/4652 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A process for producing a wiring board involves laminating a metal foil on both sides of an insulating substrate not completely cured, followed by pressing with heating; drilling holes in the resulting laminate for connecting circuits therein; removing portions of the metal foils in narrow areas around the holes to form hollow portions in the metal foils; and filling a flowable electroconductive substance in the holes and the hollow portions.

Abstract translation: 制造布线板的方法包括在未完全固化的绝缘基板的两侧层压金属箔，然后加热压制; 在所得的层压板中钻孔以在其中连接电路; 在孔周围的狭窄区域中去除金属箔的部分，以在金属箔中形成中空部分; 并在孔和中空部分填充可流动的导电物质。

公开(公告)号：US5451720A

公开(公告)日：1995-09-19

申请号：US216747

申请日：1994-03-23

Applicant: H. Scott Estes ,  David Staggs ,  Deepak Swamy

Inventor： H. Scott Estes ,  David Staggs ,  Deepak Swamy

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/34 ,  H05K3/42 ,  H05K1/00

CPC classification number: H05K1/116 ,  H05K1/0201 ,  H05K3/3447 ,  H05K2201/062 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/0969 ,  H05K3/429

Abstract: A circuit board having a thermal relief pattern for isolating heat generated during soldering of components thereon. The circuit board comprises (1) a substantially planar insulating substrate, the substrate having a via therethrough and (2) a substantially planar conductive layer located over the substrate, the via passing through the layer, the layer having a thermal relief pattern comprising a plurality of apertures located about the via, the plurality of apertures cooperating to restrict heat flow across the thermal relief pattern, each of the plurality of apertures having a boundary with the conductive layer free of discontinuities to inhibit edge effect electromagnetic resonance, the plurality of apertures defining a plurality of corresponding conductive bands in the conductive layer and between the plurality of apertures, the conductive bands cooperating to provide a predetermined minimum level of electrical conduction across the thermal relief pattern.

Abstract translation: 一种电路板，具有用于隔离焊接其内部的部件所产生的热的热释放图案。 电路板包括（1）基本平坦的绝缘基板，该基板具有穿过其中的通孔，以及（2）位于该基板上方的基本上平面的导电层，该通孔穿过该层，该层具有包括多个 位于所述通孔周围的多个孔，所述多个孔协作以限制横跨所述热浮雕图案的热流，所述多个孔中的每一个具有与所述导电层的边界，所述边界不具有不连续性，以抑制边缘效应电磁共振，所述多个孔限定 在导电层中和多个孔之间的多个对应的导电带，导电带协作以提供穿过热浮雕图案的预定的最小电导水平。

公开(公告)号：US5444189A

公开(公告)日：1995-08-22

申请号：US77722

申请日：1993-06-17

Applicant: Akishi Nakaso ,  Kouichi Tsuyama ,  Akinari Kida ,  Shuichi Hatakeyama ,  Naoyuki Urasaki

Inventor： Akishi Nakaso ,  Kouichi Tsuyama ,  Akinari Kida ,  Shuichi Hatakeyama ,  Naoyuki Urasaki

IPC: H05K3/46 ,  H05K1/09 ,  H05K1/11 ,  H05K3/00 ,  H05K3/06 ,  H05K3/40 ,  H05K1/00

CPC classification number: H05K1/116 ,  H05K3/0055 ,  H05K3/062 ,  H05K3/4069 ,  H05K1/095 ,  H05K2201/0305 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0355 ,  H05K2201/09454 ,  H05K2201/09745 ,  H05K2203/0346 ,  H05K2203/0369 ,  H05K2203/0384 ,  H05K2203/0554 ,  H05K2203/1453 ,  H05K3/06 ,  H05K3/4038 ,  H05K3/4623 ,  H05K3/4652

Abstract: A wiring board comprising one or more inner layer circuit substrates and outer circuit layers formed from metal foil layers on both sides of said dinner layer circuit substrates via prepregs, said inner layer circuit substrate comprising an insulating layer and metal foil layers formed on both sides of said insulating layer, at least one inner layer circuit substrate or said outer circuit layers or both having hollow portions in the metal foil layer filled with an electroconductive substance, said wiring board having one or more through-holes at least in the hollow portions and filled with the electroconductive substance, has high reliability and a high wiring density.

Abstract translation: 一种布线板，包括一个或多个内层电路基板和由所述晚餐层电路基板两侧的金属箔层经由预浸料形成的外部电路层，所述内层电路基板包括绝缘层和金属箔层， 所述绝缘层，至少一个内层电路基板或所述外电路层或两者在金属箔层中具有填充有导电物质的中空部分，所述布线板至少在中空部分中具有一个或多个通孔，并填充 与导电物质具有高可靠性和高布线密度。

公开(公告)号：US3102213A

公开(公告)日：1963-08-27

申请号：US2889260

申请日：1960-05-13

Applicant: HAZELTINE RESEARCH INC

Inventor： BEDSON DONALD E ,  DI NUZZO SALVATORE A ,  SULESKI ANTHONY C

IPC: H05K3/42 ,  H05K3/46

CPC classification number: H05K3/462 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/0379 ,  H05K2201/09454

公开(公告)号：EP2658353A1

公开(公告)日：2013-10-30

申请号：EP13164422.1

申请日：2013-04-19

Applicant: Canon Kabushiki Kaisha

Inventor： Hayashi, Seiji ,  Kondo, Takuya ,  Matsumoto, Shoji

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/16

CPC classification number: H05K1/0216 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/48227 ,  H05K1/0228 ,  H05K1/0242 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/114 ,  H05K1/116 ,  H05K1/14 ,  H05K1/141 ,  H05K1/162 ,  H05K1/18 ,  H05K2201/0939 ,  H05K2201/09418 ,  H05K2201/09454 ,  H05K2201/09463 ,  H05K2201/09636 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734

Abstract: First (111) and second (112) signal wiring patterns are formed in a first conductor layer (101). A first electrode pad (121) electrically connected to the first signal wiring pattern through a first via (131) and a second electrode pad (122) electrically connected to the second signal wiring pattern through a second via (132) are formed in a second conductor layer (102) as a surface layer. A third conductor layer (103) is disposed between the first conductor layer and the second conductor layer with an insulator (105) interposed between those conductor layers. A first pad (141,151,161,171) electrically connected to the first via is formed in the third conductor layer. The first pad includes an opposed portion (141a,151b,161c,171d) which overlaps the second electrode pad as viewed in a direction perpendicular to the surface of a printed board and which is opposed to the second electrode pad through intermediation of the insulator. This enables reduction of crosstalk noise caused between the signal wirings.

Abstract translation: 在第一导体层（101）中形成第一（111）和第二（112）信号布线图案。 通过第二通孔（132）通过第一通孔（131）和与第二信号布线图案电连接的第二电极焊盘（122）电连接到第一信号布线图案的第一电极焊盘（121） 导体层（102）作为表面层。 第三导体层（103）设置在第一导体层和第二导体层之间，绝缘体（105）插入在这些导体层之间。 电连接到第一通孔的第一焊盘（141,151,161,171）形成在第三导体层中。 第一焊盘包括与垂直于印刷电路板的表面的方向观察的与第二电极焊盘重叠并且通过绝缘体与第二电极焊盘相对的相对部分（141a，151b，161c，171d）。 这能够减少在信号布线之间引起的串扰噪声。

公开(公告)号：EP2499887A1

公开(公告)日：2012-09-19

申请号：EP10829414.1

申请日：2010-11-10

Applicant: ATI Technologies ULC

Inventor： LEUNG, Andrew KW

IPC: H05K3/40 ,  H05K1/11 ,  H05K3/42

CPC classification number: H05K1/115 ,  H01L24/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H05K1/113 ,  H05K1/116 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09454 ,  H05K2201/096 ,  H05K2201/10674 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first interconnect layer of a circuit board. The first interconnect layer includes first and second conductor structures in spaced apart relation, a first via in ohmic contact with the first conductor structure and a second via in ohmic contact with the second conductor structure. A second interconnect layer is formed on the first interconnect layer. The second interconnect layer includes third and fourth conductor structures in spaced apart relation and offset laterally from the first and second conductor structures, a third via in ohmic contact with the third conductor structure and a fourth via in ohmic contact with the fourth conductor structure.