公开(公告)号：US12205630B2

公开(公告)日：2025-01-21

申请号：US18005101

申请日：2020-08-24

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qing Luo ,  Bing Chen ,  Hangbing Lv ,  Ming Liu ,  Cheng Lu

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094 ,  H03K19/017

Abstract: Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.

公开(公告)号：US12198930B2

公开(公告)日：2025-01-14

申请号：US17630674

申请日：2021-11-12

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Libin Zhang ,  Yayi Wei ,  Zhen Song ,  Yajuan Su ,  Jianfang He ,  Le Ma

IPC: H01L29/40 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768

Abstract: A method for manufacturing a semiconductor device. A photolithographic coating, including a first film, a photolithographic film, and a second film, is formed on the to-be-connected structure. Refractive indexes of the first film and the second film are smaller than 1, so that the photolithographic coating forms an optical structure with a high reflection coefficient. The photolithographic coating is exposed to a light having a target wavelength through a mask. The to-be-connected structure is reflected in the photolithographic coating, and hence serves as another mask and is imaged to the photolithographic film. A pattern of the mask is simultaneously imaged to the photolithographic film. That is, both the to-be-connected structure and the pattern of the mask are imaged to a target region of the photolithographic film, and the target region corresponds to the to-be-connected structure.

公开(公告)号：US12197282B2

公开(公告)日：2025-01-14

申请号：US18553929

申请日：2021-04-08

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qianhui Li ,  Qi Wang ,  Liu Yang ,  Yiyang Jiang ,  Xiaolei Yu ,  Jing He ,  Zongliang Huo ,  Tianchun Ye

IPC: G06F11/10 ,  G06F11/14

Abstract: A data recovery method for a flash memory includes: reading data from the flash memory by using preset read voltage; calculating a check node error rate corresponding to the data; calculating a read voltage adjustment step size according to the check node error rate; adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, and repeating the operation of calculating a check node error rate corresponding to the data to operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, until the check node error rate is minimum; and selecting a read voltage corresponding to the minimum check node error rate to read data from the flash memory, so as to perform data recovery.

公开(公告)号：US12154609B2

公开(公告)日：2024-11-26

申请号：US17821783

申请日：2022-08-23

Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES

Inventor： Guozhong Xing ,  Long Liu ,  Di Wang ,  Huai Lin ,  Ming Liu

IPC: G11C11/54 ,  G11C11/16

Abstract: A magnetoresistive memory cell includes a first magnetic tunnel junction, a second magnetic tunnel junction and a metal layer. The first magnetic tunnel junction and the second magnetic tunnel junction each are disposed on the metal layer; the metal layer is configured to pass write current, a projection line of an easy axis of the first magnetic tunnel junction on a plane where the metal layer is located forms a first angle against a direction of the write current, and a projection line of an easy axis of the second magnetic tunnel junction on the plane where the metal layer is located forms a second angle against a direction opposite to the direction of the write current; the first angle and the second angle are all less than 90°; the first magnetic tunnel junction and the second magnetic tunnel junction are configured to pass read current.

公开(公告)号：US20240379764A1

公开(公告)日：2024-11-14

申请号：US18533891

申请日：2023-12-08

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang LI ,  Fei ZHAO

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A gate-all-around transistor and a method for manufacturing the same. The gate-all-around transistor comprises: a semiconductor substrate; an active structure disposed on the semiconductor substrate, where the active structure comprises a source, a drain, and a channel between the source and the drain; a doped epitaxial structure, where a portion of the semiconductor substrate beneath the channel is recessed to form a first groove, the first groove is fully filled with the doped epitaxial structure, and primary carriers of the doped epitaxial structure are opposite in polarity to primary carriers of the source and the drain; and a gate stack structure surrounding the channel, where a portion of the gate stack structure beneath the channel is disposed between the doped epitaxial structure and the channel.

公开(公告)号：US20240371637A1

公开(公告)日：2024-11-07

申请号：US18624334

申请日：2024-04-02

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU ,  Zhuo CHEN ,  Jinbiao LIU ,  Junfeng LI ,  Jun LUO

IPC: H01L21/02 ,  H01L21/8234 ,  H01L27/088

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: forming a channel defining layer and a source/drain layer sequentially on a substrate of a crystalline material; patterning the channel defining layer and the source/drain layer as a ridge protruding relative to the substrate; forming a channel layer on a sidewall of the ridge by deposition; and performing a crystallization process to recrystallize the channel layer.

公开(公告)号：US20240355921A1

公开(公告)日：2024-10-24

申请号：US18238947

申请日：2023-08-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Sen HUANG ,  Qimeng JIANG ,  Xinyue DAI ,  Xinhua WANG ,  Xinyu LIU

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7789 ,  H01L29/08 ,  H01L29/41725 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The folded channel gallium nitride based field-effect transistor includes: a base layer; a multi-heterojunction layer, including a channel layer and a barrier layer alternatingly stacked from bottom to top on a gallium nitride semi-insulating layer; a gallium nitride control layer on the multi-heterojunction layer and extending from one side of the channel region to at least a part of the groove; a current collapse suppression structure formed on the multi-heterojunction layer on another side of the channel region; a source electrode and a drain electrode that are respectively in contact with two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer; a gate electrode formed on the multi-heterojunction layer between the source electrode and the gallium nitride control layer; and a connecting structure passing over the gate electrode to electrically connect to the source electrode and the gallium nitride control layer.

公开(公告)号：US12124945B2

公开(公告)日：2024-10-22

申请号：US17310203

申请日：2019-01-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Hangbing Lv ,  Xiaoxin Xu ,  Qing Luo ,  Ming Liu

IPC: G06N3/065 ,  G11C11/22 ,  G11C11/54 ,  H01L29/51 ,  H01L29/78

CPC classification number: G06N3/065 ,  G11C11/223 ,  G11C11/2273 ,  G11C11/54 ,  H01L29/516 ,  H01L29/78391

Abstract: Disclosed is a neural network operation device, including: an operation array including operation units, wherein each operation unit includes: a source terminal, a drain terminal, a gate electrode, a threshold voltage adjustment layer under the gate electrode, and a channel region extending between a source region and a drain region, the threshold voltage adjustment layer is located on the channel region. The gate electrodes of each column of operation units of the operation array are connected together, and each column is used to adjust a weight value according to a threshold voltage adjusted by the threshold voltage adjustment layer. The threshold voltage adjustment layer is a ferroelectric layer.

公开(公告)号：US12107046B2

公开(公告)日：2024-10-01

申请号：US17597907

申请日：2019-07-31

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Gang Zhang ,  Zongliang Huo

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L23/535

Abstract: Provided is an L-shaped stepped word line structure including: L-shaped word line units, each including a long side extending in a second direction and arranged adjacent to a gate line slit, and a short side extending in a first direction. A word line terminal included in the short side is formed in a stepped stacked layer structure including stacked layer pairs formed of an insulating material, a region close to the gate line slit in a stacked layer of each stacked layer pair serves as a replacement metal region including a short side region surface/internal metal layer respectively located on a surface/in an interior. In a first direction, a length of the short side region surface metal layer is greater than that of the short side region internal metal layer, and the word line terminal corresponds to the short side region surface metal layer.

公开(公告)号：US12088323B2

公开(公告)日：2024-09-10

申请号：US18254377

申请日：2020-11-25

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Qi Wang ,  Yiyang Jiang ,  Qianhui Li ,  Zongliang Huo ,  Tianchun Ye

IPC: H03M13/39 ,  G11C29/12 ,  G11C29/42 ,  G11C29/46

CPC classification number: H03M13/3905 ,  G11C29/1201 ,  G11C29/42 ,  G11C29/46

Abstract: A read-write method includes: sequentially writing, in a first direction, a code word obtained by information-bit encoding into a target memory cell in each layer of memory cell array in the three-dimensional memory; randomly reading the target memory cell in each layer of memory cell array, or sequentially reading the target memory cell in each layer of memory cell array in a second direction; and determining an LLR value of a current target memory cell according to a storage time corresponding to the current target memory cell when reading, a threshold voltage partition corresponding to the current target memory cell when reading, a comprehensive distribution state corresponding to the current target memory cell when reading, and a pre-established LLR table, so as to perform a soft decoding operation on the code word in the current target memory cell based on the LLR value of the current target memory cell.