-
公开(公告)号：US12068757B2
公开(公告)日：2024-08-20
申请号：US17907048
申请日：2020-03-23
Inventor： Qi Wang , Yiyang Jiang , Qianhui Li , Zongliang Huo
IPC: H03M13/11 , H03M13/15 , H03M13/39 , G06F11/00 , G11C29/52 , H03M13/25 , H03M13/29 , H03M13/37 , H03M13/45
CPC classification number: H03M13/1111 , H03M13/154 , H03M13/3927 , G06F11/00 , G11C29/52 , H03M13/1108 , H03M13/255 , H03M13/2948 , H03M13/3746 , H03M13/45
Abstract: The method includes: reading a memory cell having a encoded information bit, so as to obtain an LLR value of a current memory cell with reference to a pre-established LLR table according to a storage time, a threshold voltage partition and a comprehensive distribution corresponding to the current memory cell during reading; and performing a soft decoding operation on a codeword in the memory cell having the encoded information bit according to the read LLR value of the current memory cell, wherein the comprehensive distribution of the current memory cell is determined according to an influence of a memory cell adjacent to the current memory cell on a distribution of the current memory cell; an input of the pre-established LLR table comprises a storage time, a threshold voltage partition and a comprehensive distribution, and an output of the pre-established LLR table comprises an LLR value.
-
172.发明公开公开(公告)号：US20240258386A1
公开(公告)日：2024-08-01
申请号：US18289998
申请日：2022-04-20
Inventor： Huilong Zhu
IPC: H01L29/417 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC classification number: H01L29/41733 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696
Abstract: Disclosed are a semiconductor apparatus, a manufacturing method, and an electronic device. The semiconductor apparatus includes first and second devices vertically stacked. Each of the first and second devices includes a first source/drain layer, a channel layer and a second source/drain layer vertically stacked, and a gate stack surrounding a periphery of the channel layer. The first device protrudes in a first direction relative to the second device to form a first step. A second step is defined by the second device. On a side in a second direction intersecting with the first direction, the first source/drain layer of each device protrudes in the second direction relative to the second source/drain layer and gate stack, to form a sub-step. Each sub-step is on a corresponding step. On another side in the second direction, the gate stack of each device protrudes in the second direction relative to the second source/drain layer.
-
公开(公告)号：US20240220355A1
公开(公告)日：2024-07-04
申请号：US18553929
申请日：2021-04-08
Inventor： Qianhui LI , Qi WANG , Liu YANG , Yiyang JIANG , Xiaolei YU , Jing HE , Zongliang HUO , Tianchun YE
IPC: G06F11/10
CPC classification number: G06F11/1008
Abstract: A data recovery method for a flash memory includes: reading data from the flash memory by using preset read voltage; calculating a check node error rate corresponding to the data; calculating a read voltage adjustment step size according to the check node error rate; adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, and repeating the operation of calculating a check node error rate corresponding to the data to operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, until the check node error rate is minimum; and selecting a read voltage corresponding to the minimum check node error rate to read data from the flash memory, so as to perform data recovery.
-
公开(公告)号：US20240176228A1
公开(公告)日：2024-05-30
申请号：US17773668
申请日：2021-11-08
Inventor： Jianfang HE , Yayi WEI , Yajuan SU , Lisong DONG , Libin ZHANG , Rui CHEN , Le MA
Abstract: The present disclosure provides a method for optimizing mask parameters, and the method includes: acquiring a test pattern, light source parameters, and initial mask parameters, the initial mask parameters including a mask thickness and an initial mask sidewall angle; generating multiple sets of candidate mask parameters according to the initial mask sidewall angle in the initial mask parameters; the multiple sets of candidate mask parameters including different mask sidewall angles and the same mask thickness; obtaining an imaging contrast of each set of candidate mask parameters based on the test pattern and the light source parameters; and selecting an optimal mask sidewall angle from the multiple sets of candidate mask parameters according to the imaging contrasts. By generating multiple sets of candidate mask parameters including different mask sidewall angles and the same mask thickness, and simulating these sets of candidate mask parameters respectively, the imaging contrast of each set of candidate mask parameters is obtained, so that the optimal mask sidewall angle is found according to the imaging contrasts. Therefore, by optimizing the mask parameters of the multi-layer film lens structure, the imaging contrast can also be significantly improved, and the imaging resolution can be improved.
-
175.发明授权公开(公告)号：US11942474B2
公开(公告)日：2024-03-26
申请号：US18172802
申请日：2023-02-22
Inventor： Huilong Zhu
IPC: H01L29/66 , H01L21/77 , H01L25/065 , H01L27/088 , H01L29/78
CPC classification number: H01L27/088 , H01L21/77 , H01L25/0657 , H01L29/66712 , H01L29/7802
Abstract: A method of manufacturing a parallel structure of semiconductor devices includes: disposing a semiconductor stack, which includes source/drain layers disposed vertically in sequence and channel layers therebetween, on a substrate; patterning the semiconductor stack into a predetermined shape to define an active region; forming gate stacks around at least part of peripheries of the channel layers; forming an isolation layer on peripheries of the active region and the gate stack; forming first to third conductive channels on a sidewall of the isolation layer; determining the pre-determined shape and a shape of the gate stacks, such that one of the source/drain layers on two sides of the channel layer passes through the isolation layer to contact the first conductive channel, while the other one passes through the isolation layer to contact the second conductive channel, and the gate stack passes through the isolation layer to contact the third conductive channel.
-
Patent Agency Ranking
公开(公告)号：US11930720B2
公开(公告)日：2024-03-12
申请号：US17495390
申请日：2021-10-06
Inventor： Meiyin Yang , Jun Luo , Yan Cui , Jing Xu
CPC classification number: H10N52/80 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/18 , G11C11/22 , H10B61/00 , H10N52/00 , G11C11/1659
Abstract: The present disclosure provides a storage unit, a data writing method and a data reading method thereof, a memory and an electronic device. The storage unit includes a semiconductor substrate, a first insulating medium layer, a ferroelectric thin film layer, a bottom electrode, a tunnel junction, a first metal interconnection portion, a second metal interconnection portion, a third metal interconnection portion and a fourth metal interconnection portion. The first insulating medium layer is formed on the semiconductor substrate, the ferroelectric thin film layer is disposed on the first insulating medium layer, the bottom electrode is formed on the ferroelectric thin film layer, and the tunnel junction is formed on the bottom electrode. The first metal interconnection portion is connected to a first end of the bottom electrode, and the third metal interconnection portion is connected to a second end of the bottom electrode. The second metal interconnection portion is connected to the ferroelectric thin film layer, and the fourth metal interconnection portion is connected to the tunnel junction. As compared with the prior art, the present disclosure can control a directional flipping of the magnetic moment in the tunnel junction based on the ferroelectric thin film layer provided. Based on the structural design of the storage unit, the present disclosure does not require an external magnetic field, and fully meets the requirement of high integration of the device.
-
公开(公告)号：US11929304B2
公开(公告)日：2024-03-12
申请号：US17666790
申请日：2022-02-08
Inventor： Huilong Zhu , Tianchun Ye
CPC classification number: H01L23/46 , H01L21/4871
Abstract: A semiconductor apparatus with a heat dissipation conduit in a sidewall interconnection structure, a method of manufacturing the semiconductor apparatus, and an electronic device including the semiconductor apparatus. According to the embodiments, the semiconductor apparatus includes: a carrier substrate having a first region and a second region adjacent to each other; a semiconductor device on the first region; and an interconnection structure on the second region, wherein the interconnection structure includes: an electrical isolation layer; a conductive structure in the electrical isolation layer, wherein at least a part of components require to be electrically connected in the semiconductor device is in contact with and therefore electrically connected to the conductive structure in a lateral direction, wherein the conductive structure is located at a corresponding height in the interconnection structure; and a heat dissipation conduit in the electrical isolation layer.
-
公开(公告)号：US20240071451A1
公开(公告)日：2024-02-29
申请号：US18261716
申请日：2021-01-21
Inventor： Huai LIN , Guozhong XING , Zuheng WU , Long LIU , Di WANG , Cheng LU , Peiwen ZHANG , Changqing XIE , Ling LI , Ming LIU
IPC: G11C11/16
CPC classification number: G11C11/1673 , G11C11/1655 , G11C11/1657
Abstract: The three-state spintronic device includes: a bottom electrode, a magnetic tunnel junction and a top electrode from bottom to top. The magnetic tunnel junction includes: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers and domain wall nucleation centers. An antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in an interface between a heavy metal and the ferromagnetic free layer. The magnetic domain wall nucleation centers are at two ends of the ferromagnetic free layer. A current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under a control of all-electrical controlled, an effective field of a spin-orbit torque drives domain wall to move and displace.
-
179.发明公开公开(公告)号：US20240038318A1
公开(公告)日：2024-02-01
申请号：US18254377
申请日：2020-11-25
Inventor： Qi Wang , Yiyang Jiang , Qianhui Li , Zongliang Huo , Tianchun Ye
CPC classification number: G11C29/42 , G11C29/46 , G11C29/1201
Abstract: A read-write method includes: sequentially writing, in a first direction, a code word obtained by information-bit encoding into a target memory cell in each layer of memory cell array in the three-dimensional memory; randomly reading the target memory cell in each layer of memory cell array, or sequentially reading the target memory cell in each layer of memory cell array in a second direction; and determining an LLR value of a current target memory cell according to a storage time corresponding to the current target memory cell when reading, a threshold voltage partition corresponding to the current target memory cell when reading, a comprehensive distribution state corresponding to the current target memory cell when reading, and a pre-established LLR table, so as to perform a soft decoding operation on the code word in the current target memory cell based on the LLR value of the current target memory cell.
-
公开(公告)号：US20240005077A1
公开(公告)日：2024-01-04
申请号：US18250461
申请日：2020-10-30
Inventor： Nianduan Lu , Ling Li , Wenfeng Jiang , Di GENG , Jiawei Wang , Ming Liu
CPC classification number: G06F30/39 , G16C60/00 , H01L29/786
Abstract: A method of designing a thin film transistor device, including: calculating characteristic parameters of searched materials; screening the materials according to a characteristic parameter threshold to obtain first active layer materials; simulating the first active layer material as an active layer material in a thin film transistor device model to obtain a device characteristic of the thin film transistor device; screening the first active layer materials according to a device characteristic threshold to obtain second active layer materials; taking the second active layer material as the active layer material of the thin film transistor device to perform an experiment; and selecting another second active layer material to perform the experiment once again when an experiment result does not meet a preset requirement, and a design of the thin film transistor device is completed until the experiment result meets the preset requirement.
-
-
-
-
-
-
-
-
-
Search Results
761
records
(took 0.036 seconds)
