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公开(公告)号：KR1020130026627A
公开(公告)日：2013-03-14
申请号：KR1020110089637
申请日：2011-09-05
Applicant: 한국전자통신연구원
IPC: H03M1/46
CPC classification number: H03M1/462
Abstract: PURPOSE: An analog-digital conversion device and a conversion method using clock delay are provided to reduce SAR(Successive Approximation Register) conversion time and to improve operation speed without additional power or area consumption. CONSTITUTION: An analog-digital conversion device(100) includes a clock delay adjustment unit(110), a clock generation unit(120), an SAR logical unit(130), a capacitive digital-analog conversion unit(150), and a comparison unit(140). The clock generation unit generates a clock signal. The clock delay adjustment unit outputs a first clock signal to a K clock signal. The capacitive digital-analog conversion unit receives an analog signal and a reference voltage and outputs a difference between the analog signal and the reference voltage. The comparison unit determines the output of the capacitive digital-analog conversion unit in response to the output of the clock delay adjustment unit. The SAR logical unit outputs an N-bits digital signal by performing a successive approximation operation. [Reference numerals] (110) Clock delay adjustment unit; (120) Clock generation unit; (130) SAR logical unit; (140) Comparison unit; (AA) Digital signal; (BB) Analog signal; (CC) Reference voltage
Abstract translation: 目的：提供使用时钟延迟的模拟数字转换器件和转换方法，以减少SAR（连续近似寄存器）转换时间，并提高运算速度，而无需额外的电源或面积消耗。 构成：模拟数字转换装置（100）包括时钟延迟调整单元（110），时钟生成单元（120），SAR逻辑单元（130），电容数字模拟转换单元（150）和 比较单元（140）。 时钟生成单元生成时钟信号。 时钟延迟调整单元将第一时钟信号输出到K时钟信号。 电容数字 - 模拟转换单元接收模拟信号和参考电压，并输出模拟信号和参考电压之间的差值。 比较单元响应于时钟延迟调整单元的输出来确定电容数字 - 模拟转换单元的输出。 SAR逻辑单元通过执行逐次逼近操作来输出N位数字信号。 （附图标记）（110）时钟延迟调整单元; （120）时钟发生单元; （130）SAR逻辑单元; （140）比较单位; （AA）数字信号; （BB）模拟信号; （CC）参考电压
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公开(公告)号：KR1020130012449A
公开(公告)日：2013-02-04
申请号：KR1020110073670
申请日：2011-07-25
Applicant: 한국전자통신연구원
CPC classification number: H03K4/501 , H03K4/00 , H03K4/06 , H03K4/08 , H03K4/12 , H03K4/48 , H03K4/50
Abstract: PURPOSE: A triangular waveform generator capable of regulating the pulse width of triangular waves for having various duty ratios and a triangular wave generation method thereof are provided to minimize the number of elements necessary for triangular wave generation, thereby simplifying a total structure. CONSTITUTION: A square wave signal generator(110) generates a square wave signal for the generation of triangular waves. A triangular wave generator(100) is able to generate the square wave signal in response to a reset signal. A resistance unit(120) is connected between the square wave signal generator and a capacitor unit(130). The resistance unit is able to control the voltage level of the square wave signal. The capacitor unit generates a triangular wave signal by using the square wave signal. The capacitor unit includes variable capacitors. The capacitor unit receives the square wave signal outputted from a transistor connected to an output terminal.
Abstract translation: 目的：提供能够调节用于具有各种占空比的三角波的脉冲宽度的三角波形发生器及其三角波产生方法，以最小化三角波产生所需的元件数量，从而简化总体结构。 构成：方波信号发生器（110）产生用于产生三角波的方波信号。 三角波发生器（100）能够响应于复位信号产生方波信号。 电阻单元（120）连接在方波信号发生器和电容器单元（130）之间。 电阻单元能够控制方波信号的电压电平。 电容器单元通过使用方波信号产生三角波信号。 电容器单元包括可变电容器。 电容器单元接收从连接到输出端子的晶体管输出的方波信号。
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公开(公告)号：KR101201892B1
公开(公告)日：2012-11-16
申请号：KR1020090072660
申请日：2009-08-07
Applicant: 한국전자통신연구원
Abstract: 본 발명은 디지털-아날로그 변환기에 대한 것으로, 이 장치는 양의 변환부, 음의 변환부, 그리고 상기 양의 변환부 및 상기 음의 변환부의 출력을 입력받아 기준 전압과 비교하여 출력 전압을 생성하는 비교기를 포함하며, 상기 양의 변환부 및 상기 음의 변환부는 상위비트의 각 비트에 대응하는 복수의 비트 커패시터를 포함하는 상위비트 변환부, 하위비트의 각 비트에 대응하는 복수의 비트 커패시터를 포함하는 하위비트 변환부, 그리고 상기 상위비트 변환부 및 상기 하위비트 변환부를 직렬 연결하는 커플링 커패시터를 포함하며, 상기 양의 변환부 및 음의 변환부는 각 비트의 변환 시 동일한 오프셋을 갖도록 바이어스 전압을 인가받는다. 따라서 작은 면적으로 큰 해상도를 얻을 수 있으며, 커패시터의 개수를 줄일 수 있어 단위 커패시터의 정전용량을 최대화 할 수 있기 때문에 열 노이즈 및 소자의 부정합을 최소화 할 수 있다.
의사 차동 디지털-아날로그 변환기, 병합 커패시터, 순차 접근 아날로그-디지털 변환기-
公开(公告)号：KR1020120047379A
公开(公告)日：2012-05-14
申请号：KR1020100108683
申请日：2010-11-03
Applicant: 한국전자통신연구원
CPC classification number: H03L7/1976 , H03L7/0891
Abstract: PURPOSE: A spread spectrum clock generator is provided to generate a spreading spectrum clock by controlling a division ratio using a digital signal. CONSTITUTION: A phase detector(110) receives a reference frequency signal and a frequency division signal. The phase detector detects the phase difference of the reference frequency signal and the frequency division signal. A charge pump(120) generates an electric charge or a current in response to the output of the phase detector. A loop filter(130) includes a capacitor. A voltage control oscillator(140) generates an oscillation signal corresponding to the output voltage of the loop filter. A main divider(150) receives the oscillation signal from the voltage control oscillator. The main divider divides the oscillation signal according to a certain division ratio. A division ratio controller(170) comprises a triangle wave generator(172), a delta-sigma modulator(174), a sub divider(176), and a summer(178).
Abstract translation: 目的：提供扩频时钟发生器，通过使用数字信号控制分频比来产生扩展频谱时钟。 构成：相位检测器（110）接收参考频率信号和分频信号。 相位检测器检测参考频率信号和分频信号的相位差。 电荷泵（120）响应于相位检测器的输出产生电荷或电流。 环路滤波器（130）包括电容器。 电压控制振荡器（140）产生对应于环路滤波器的输出电压的振荡信号。 主分压器（150）从压控振荡器接收振荡信号。 主分压器根据一定的分频比划分振荡信号。 分频比控制器（170）包括三角波发生器（172），Δ-Σ调制器（174），子分频器（176）和加法器（178）。
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公开(公告)号：KR1020120025660A
公开(公告)日：2012-03-16
申请号：KR1020100087630
申请日：2010-09-07
Applicant: 한국전자통신연구원
CPC classification number: H03L7/083 , H03J2200/10 , H03L7/0891 , H03L7/0995 , H03L7/187
Abstract: PURPOSE: A phase locked loop circuit including an automatic frequency control circuit and an operating method thereof are provided to reduce time for fixing a arbitrary output frequency by including an automatic frequency control circuit which performs fast operation. CONSTITUTION: A phase detector(110) detects the phase or frequency difference of a divided oscillation signal and a reference frequency signal. A charge pump(120) generates an electric charge or current in response to the output of the phase detector. A loop filter(130) includes a capacitor. The capacitor of the loop filter is charged or discharged according to the output of the charge pump. A voltage control oscillator(140) generates an oscillation signal having a frequency corresponding to an output voltage in response to the output voltage of the loop filter. A divider(150) lowers the frequency of the oscillation signal outputted from the voltage control oscillator as much as a division ratio. An automatic frequency control circuit(160) outputs at least one or more digital code bits.
Abstract translation: 目的：提供一种包括自动频率控制电路及其操作方法的锁相环电路，通过包括执行快速操作的自动频率控制电路来减少固定任意输出频率的时间。 构成：相位检测器（110）检测分频振荡信号和基准频率信号的相位或频率差。 电荷泵（120）响应于相位检测器的输出产生电荷或电流。 环路滤波器（130）包括电容器。 环路滤波器的电容器根据电荷泵的输出进行充放电。 电压控制振荡器（140）响应于环路滤波器的输出电压产生具有对应于输出电压的频率的振荡信号。 分压器（150）将从压控振荡器输出的振荡信号的频率降低到分频比。 自动频率控制电路（160）输出至少一个或多个数字码位。
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Patent Agency Ranking
公开(公告)号：KR1020110067674A
公开(公告)日：2011-06-22
申请号：KR1020090124366
申请日：2009-12-15
Applicant: 한국전자통신연구원
CPC classification number: H04N19/436 , H04N19/44 , G06F9/3885 , G06F9/382 , G06F12/0835 , G06F13/36 , H04N19/48
Abstract: PURPOSE: A pipelined decoding apparatus and a method based on parallel processing are provided to increase the performance of decoding by enabling the mass data transmission to be pipelined while executing parallel processing in a macro-block unit. CONSTITUTION: A bit stream processor(301) performs a context-adaptive variable length adaptive coding(CAVLC) to the compressed bit stream, and then decodes macro-block header and coefficients. A parallel processing array processor(303) processes inverse quantization, inverse transformation and movement compensation operation for the macro blocks in parallel using the decoded macro block header / count values. A sequential processing processor(304) processes an intra prediction and deblocking filter operation for the macro blocks in sequence.
Abstract translation: 目的：提供一种流水线解码装置和基于并行处理的方法，以通过在宏块单元中执行并行处理时使质量数据传输被流水线化来提高解码性能。 构成：比特流处理器（301）对压缩比特流执行上下文自适应可变长度自适应编码（CAVLC），然后解码宏块头部和系数。 并行处理阵列处理器（303）使用解码的宏块头/计数值并行处理宏块的逆量化，逆变换和移动补偿操作。 顺序处理处理器（304）按顺序处理宏块的帧内预测和去块滤波操作。
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公开(公告)号：KR101020513B1
公开(公告)日：2011-03-09
申请号：KR1020080087332
申请日：2008-09-04
Applicant: 한국전자통신연구원
CPC classification number: H03L7/095
Abstract: 본 발명에 따른 락 검출 회로는 2개의 지연 소자, 4개의 플립플롭, 2개의 논리 게이트로 구현이 가능하면서 PLL 회로의 락 상태를 정확하게 검출할 수 있다. 따라서, 락 검출 회로를 간단한 구조로 구현할 수 있으므로, 이에 따라 락 검출 회로의 소형화를 도모할 수 있으며 소비전력을 감소시킬 수 있다. 또한, 본 발명에 따른 락 검출 방법에 의하면, 락 상태를 검출하는 과정이 간단해지므로 빠른 시간내에 락 상태를 검출할 수 있다.
PLL(위상고정루프), 락(lock), 위상 주파수 검출기(PFD)-
公开(公告)号：KR1020110011511A
公开(公告)日：2011-02-08
申请号：KR1020100020194
申请日：2010-03-08
Applicant: 한국전자통신연구원
CPC classification number: H03B5/24 , H03B5/1215 , H03B5/1228 , H03B5/1265 , H03B2200/009
Abstract: PURPOSE: An LC voltage controlled generator is provided to reduce a power value in a specific offset frequency by improving the flicker noise of the LC voltage controlled generator. CONSTITUTION: An LC resonance circuit(210) comprises an inductor connected to a power terminal, a capacitor having a parallel connection with the inductor, and a variable capacitor which is connected in parallel between the inductor and the capacitor. An amplification circuit(220) includes a pair of negative boosting transistors and a pair of switching transistors. The gate node of the switching transistor is connected to a bias voltage through each resistor. A bias voltage supply circuit(230) comprises a current source and a transistor. The gate of the transistor has a constant DC voltage through a current source in the bias voltage supply circuit.
Abstract translation: 目的：提供LC电压控制发生器，通过提高LC电压控制发电机的闪烁噪声来降低特定偏移频率的功率值。 构成：LC谐振电路（210）包括连接到电源端子的电感器，与电感器并联的电容器，以及并联连接在电感器和电容器之间的可变电容器。 放大电路（220）包括一对负升压晶体管和一对开关晶体管。 开关晶体管的栅极节点通过每个电阻器连接到偏置电压。 偏置电压供给电路（230）包括电流源和晶体管。 晶体管的栅极通过偏压电源电路中的电流源具有恒定的直流电压。
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公开(公告)号：KR1020100071630A
公开(公告)日：2010-06-29
申请号：KR1020080130418
申请日：2008-12-19
Applicant: 한국전자통신연구원
CPC classification number: H04R3/00
Abstract: PURPOSE: A read-out circuit with high impedance is provided to implement an integrated one chip by forming a preamp with a resistor and an amplifier. CONSTITUTION: An amplifier(330) has an amplifying gain between 0 and 1. A feedback resistor(Ro) is connected between an input terminal(340) and an output terminal(350) of an amplifier. As the amplifying gain of the amplifier becomes 1, the input impedance is high. The amplifier is comprised of a unit gain amplifier using the operational amplifier. The operational amplifier comprises a positive input terminal, a negative input terminal, and output terminal. The output terminal of the operational amplifier is connected to the negative input terminal.
Abstract translation: 目的：提供高阻抗的读出电路，通过与电阻和放大器形成前置放大器来实现集成的一个芯片。 构成：放大器（330）具有在0和1之间的放大增益。反馈电阻（Ro）连接在放大器的输入端（340）和输出端（350）之间。 当放大器的放大增益变为1时，输入阻抗很高。 放大器由使用运算放大器的单位增益放大器组成。 运算放大器包括正输入端，负输入端和输出端。 运算放大器的输出端连接到负输入端。
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公开(公告)号：KR1020100031831A
公开(公告)日：2010-03-25
申请号：KR1020080090653
申请日：2008-09-16
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A multi-stage successive approximation register analog to digital converter and an analog to digital conversion method thereof are provided to reduce analog to digital conversion time by improving an analog to digital conversion method. CONSTITUTION: A first SAR(Successive Approximation Register) ADC(300) changes a first analog input voltage to a n-bit digital. A second SAR ADC(310) changes the residual voltage of the first SAR ADC to a m-bit digital. The first SAR ADC changes the second analog input voltage to a digital during the residual voltage digital conversion period of the second SAR ADC.
Abstract translation: 目的：提供多级逐次逼近寄存器模数转换器及其模/数转换方法，以通过改进模数转换方法来减少模数转换时间。 构成：第一个SAR（逐次逼近寄存器）ADC（300）将第一个模拟输入电压更改为n位数字。 第二个SAR ADC（310）将第一个SAR ADC的残余电压改变为m位数字。 在第二个SAR ADC的剩余电压数字转换周期期间，第一个SAR ADC将第二个模拟输入电压改变为数字。
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