公开(公告)号：US20150223361A1

公开(公告)日：2015-08-06

申请号：US14260007

申请日：2014-04-23

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hyun LIM ,  Jong In RYU ,  Sun Ho KIM ,  Eun Jung JO ,  Kyu Hwan OH ,  Do Jae YOO

IPC: H05K7/02 ,  H05K13/04 ,  H05K3/34

CPC classification number: H05K3/3478 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/111 ,  H05K1/115 ,  H05K3/0052 ,  H05K3/284 ,  H05K3/321 ,  H05K3/4015 ,  H05K2201/09409 ,  H05K2201/09436 ,  H05K2201/10318 ,  H05K2201/10424 ,  H05K2201/10787 ,  H05K2203/0228 ,  H05K2203/1316 ,  H01L2924/00012

Abstract: There are provided an electronic component module capable of increasing a degree of integration by mounting electronic components on both surfaces of a substrate, and a manufacturing method thereof. The electronic component module according to an exemplary embodiment of the present disclosure includes: a substrate; a plurality of electronic components mounted on both surfaces of the substrate; connection conductors each having one end bonded to one surface of the substrate using an conductive adhesive; and a molded portion having the connection conductor embedded therein and formed on one surface of the substrate, wherein the connection conductor may have at least one blocking member preventing a spread of the conductive adhesive.

Abstract translation: 提供一种能够通过将电子部件安装在基板的两个表面上而提高集成度的电子部件模块及其制造方法。 根据本公开的示例性实施例的电子部件模块包括：基板; 安装在所述基板的两个表面上的多个电子部件; 连接导体各自具有使用导电粘合剂结合到基板的一个表面的一端; 以及模制部分，其具有嵌入其中并且形成在基板的一个表面上的连接导体，其中连接导体可以具有防止导电粘合剂扩散的至少一个阻挡构件。

公开(公告)号：US08796825B2

公开(公告)日：2014-08-05

申请号：US13353217

申请日：2012-01-18

Applicant: Ravindra V. Tanikella

Inventor： Ravindra V. Tanikella

IPC: H01L23/58 ,  H01L23/12 ,  H01L23/52

CPC classification number: H01L23/49894 ,  C08F283/04 ,  C08G73/121 ,  C08K3/36 ,  C08K9/10 ,  C08K2201/011 ,  C08L79/08 ,  C08L2666/66 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15791 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/28 ,  H05K3/421 ,  H05K3/422 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/1163 ,  H05K2203/121 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening.

Abstract translation: 用于微电子封装的高度可靠的互连。 在一个实施例中，积聚互连中的电介质层具有玻璃化转变温度的等级; 并且稍后施加的电介质层在低于较早施加的电介质层的玻璃化转变温度的温度下被层压。 在一个实施方案中，通过热固化工艺增加了积聚互连中早期施加的介电膜的玻璃化转变温度，以超过用于层压后来施加的电介质膜的温度。 在一个实施方案中，在层压聚酰亚胺材料的膜（例如，通过催化剂的密封剂的光化学或热降解）之后，用嵌入的催化剂形成聚酰亚胺材料以促进交联。 在一个实施例中，阻焊剂开口壁具有通过激光辅助接种产生的可湿性层，使得阻焊剂开口壁之间没有间隙，并且在阻焊剂开口中没有底部填充物。

公开(公告)号：US20140003015A1

公开(公告)日：2014-01-02

申请号：US14016707

申请日：2013-09-03

Applicant: Shinji WATANABE ,  Nobuhiro MIKAMI ,  Junya SATO ,  Kenichiro FUJII ,  Katsumi ABE ,  Atsumasa SAWADA

Inventor： Shinji WATANABE ,  Nobuhiro MIKAMI ,  Junya SATO ,  Kenichiro FUJII ,  Katsumi ABE ,  Atsumasa SAWADA

IPC: H05K1/18

CPC classification number: H05K1/18 ,  H01L24/18 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1515 ,  H01L2924/15151 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/023 ,  H05K1/0271 ,  H05K1/0284 ,  H05K1/185 ,  H05K1/189 ,  H05K3/0014 ,  H05K3/32 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/09018 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09436 ,  H05K2201/10477 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10734 ,  H05K2203/1469 ,  H05K2203/302 ,  Y02P70/611 ,  H01L2924/00

Abstract: An object of the present invention is to allow stress that may be applied to a semiconductor package to be suppressed, when the semiconductor package is mounted on a curved board. In a mount board 1, a semiconductor package 20 is mounted on a curved board 10 including a curved surface on at least a portion thereof. The curved board 10 includes a pedestal portion 13a disposed on a region of the curved surface portion where the semiconductor package 20 is mounted and having an upper surface thereof formed flat, and a plurality of pad portions 15a disposed on the flat surface of the pedestal portion 13a. The pedestal portion 13a is formed of an insulating material. The semiconductor package 20 is mounted on the pad portions 15a.

Abstract translation: 本发明的目的在于，当将半导体封装安装在弯曲的基板上时，可以抑制对半导体封装件施加的应力。 在安装基板1中，将半导体封装20安装在其至少一部分上包括弯曲表面的弯曲板10上。 弯曲板10包括设置在半导体封装20安装的弯曲表面部分的区域上并具有平坦的上表面的基座部分13a和设置在基座部分的平坦表面上的多个焊盘部分15a 13a。 基座部分13a由绝缘材料形成。 半导体封装20安装在焊盘部分15a上。

公开(公告)号：US20130256023A1

公开(公告)日：2013-10-03

申请号：US13853534

申请日：2013-03-29

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Eung Soo Kim

IPC: H05K3/10 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K3/10 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/02 ,  H05K1/111 ,  H05K1/113 ,  H05K3/108 ,  H05K3/4644 ,  H05K2201/09436 ,  H05K2201/09827 ,  Y02P70/611 ,  Y10T156/1062 ,  H01L2924/00

Abstract: Disclosed herein is a printed circuit board, including: a base substrate having an outer layer circuit; an insulating layer formed partially on the base substrate; and a circuit layer formed on the insulating layer.

Abstract translation: 这里公开了一种印刷电路板，包括：具有外层电路的基底基板; 绝缘层，部分地形成在所述基底基板上; 以及形成在所述绝缘层上的电路层。

公开(公告)号：US08487432B2

公开(公告)日：2013-07-16

申请号：US12907430

申请日：2010-10-19

Applicant: Glenn A. Rinne ,  J. Daniel Mis

Inventor： Glenn A. Rinne ,  J. Daniel Mis

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05178 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05557 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/062 ,  H05K3/243 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2203/054 ,  H05K2203/0723 ,  H01L2924/00014 ,  H01L2924/013

Abstract: An electronic device may include a substrate, a seed layer on the substrate, a barrier layer on the seed layer opposite the substrate, and an oxidation barrier on the barrier layer opposite the seed layer. The barrier layer and the seed layer comprise different materials, and the oxidation barrier and the barrier layer may comprise different materials. The seed layer may be undercut relative to the barrier layer and/or relative to the oxidation barrier so that the barrier layer and/or the oxidation barrier define a lip extending beyond the seed layer in a direction parallel with respect to a surface of the substrate. Related methods are also discussed.

Abstract translation: 电子器件可以包括衬底，衬底上的种子层，与衬底相对的种子层上的阻挡层以及与种子层相对的阻挡层上的氧化屏障。 阻挡层和种子层包含不同的材料，氧化屏障和阻挡层可以包括不同的材料。 种子层可以相对于阻挡层和/或相对于氧化屏障而被切削，使得阻挡层和/或氧化屏障在相对于衬底的表面平行的方向上限定延伸超过种子层的唇缘 。 还讨论了相关方法。

公开(公告)号：US08302298B2

公开(公告)日：2012-11-06

申请号：US12835085

申请日：2010-07-13

Applicant: Chen-Yueh Kung ,  Wei-Cheng Chen

Inventor： Chen-Yueh Kung ,  Wei-Cheng Chen

IPC: H01K3/10

CPC classification number: H05K3/4007 ,  H05K3/0035 ,  H05K3/108 ,  H05K3/421 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09436 ,  H05K2201/09545 ,  H05K2203/308 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A process for fabricating a circuit substrate is provided. A patterned conductive layer having an inner pad is provided on a base layer, a dielectric layer is disposed on the base layer and covers the patterned conductive layer, and a covering layer is disposed on the dielectric layer. A part of the covering layer is removed by dry etching to form a first opening. A part of the dielectric layer exposed by the first opening is removed to form a dielectric opening exposing a part of the inner pad. A patterned mask having a second opening to expose a part of the inner pad is formed on the covering layer. A conductive structure including a conductive block filling the dielectric opening, an outer pad filling the first opening and a surplus layer filling the second opening is formed. Finally, the patterned mask, surplus layer and covering layer are removed.

Abstract translation: 提供了一种用于制造电路基板的工艺。 具有内垫的图案化导电层设置在基底层上，电介质层设置在基底层上并覆盖图案化的导电层，并且覆盖层设置在电介质层上。 通过干蚀刻去除覆盖层的一部分以形成第一开口。 去除由第一开口暴露的电介质层的一部分，以形成暴露一部分内垫的电介质开口。 在覆盖层上形成具有第二开口以露出内部衬垫的一部分的图案化掩模。 形成包括填充电介质开口的导电块，填充第一开口的外垫和填充第二开口的剩余层的导电结构。 最后，去除图案化掩模，剩余层和覆盖层。

公开(公告)号：US20120267155A1

公开(公告)日：2012-10-25

申请号：US13543547

申请日：2012-07-06

Applicant: Chen-Yueh Kung

Inventor： Chen-Yueh Kung

IPC: H05K1/11

CPC classification number: H05K3/4007 ,  H01L2924/0002 ,  H05K3/0035 ,  H05K3/062 ,  H05K3/108 ,  H05K3/243 ,  H05K3/28 ,  H05K3/421 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09436 ,  H05K2201/09545 ,  H05K2203/0361 ,  H05K2203/0554 ,  H05K2203/0574 ,  H05K2203/1152 ,  H05K2203/308 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A circuit substrate includes a base layer, a patterned conductive layer, a dielectric layer, an outer pad and a conductive block. The patterned conductive layer is disposed on the base layer and has an inner pad. The dielectric layer is disposed on the base layer and covers the patterned conductive layer. The outer pad is disposed on the dielectric layer. The conductive layer is passed through the dielectric layer and connected between the outer pad and the inner pad, wherein the outer pad and the conductive block are formed as an integrative unit, and an outer diameter of the outer pad is substantially equal to an outer diameter of the conductive block.

Abstract translation: 电路基板包括基底层，图案化导电层，电介质层，外部焊盘和导电块。 图案化导电层设置在基底层上并具有内部衬垫。 电介质层设置在基底层上并覆盖图案化的导电层。 外垫设置在电介质层上。 导电层通过电介质层并连接在外焊盘和内焊盘之间，其中外焊盘和导电块形成为整体单元，外焊盘的外径基本上等于外焊盘 的导电块。

公开(公告)号：US20120175265A1

公开(公告)日：2012-07-12

申请号：US13426461

申请日：2012-03-21

Applicant: Sao-Hsia Tang ,  Ying-Tung Wang

Inventor： Sao-Hsia Tang ,  Ying-Tung Wang

IPC: H05K3/00 ,  C25D5/02

CPC classification number: H05K3/3452 ,  H01L23/49811 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13017 ,  H01L2224/13018 ,  H05K3/243 ,  H05K3/3473 ,  H05K3/3484 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2203/054 ,  H05K2203/0577 ,  H05K2203/0594 ,  Y10T29/49124 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01024

Abstract: A circuit board surface structure and a fabrication method thereof are proposed. The circuit board surface structure includes: a circuit board having a plurality of electrically connecting pads formed on at least one surface thereof; a first and a second insulating protective layers formed on the surface of the circuit board in sequence; first and a second openings respectively formed in the first and second insulating protective layers to expose the electrically connecting pads on the surface of the circuit board, wherein the first and second openings have narrow top and wide bottom and the diameter of the first openings is bigger than that of the second openings; and conductive elements formed in the first and second openings on surfaces of the electrically connecting pads. The present structure facilitates to strengthen the bonding between the conductive elements and the corresponding electrically connecting pads.

Abstract translation: 提出了一种电路板表面结构及其制造方法。 电路板表面结构包括：具有形成在其至少一个表面上的多个电连接焊盘的电路板; 依次形成在电路板的表面上的第一和第二绝缘保护层; 分别形成在第一和第二绝缘保护层中的第一和第二开口以暴露电路板表面上的电连接焊盘，其中第一和第二开口具有窄的顶部和宽底部，并且第一开口的直径较大 比第二个开口; 以及形成在电连接焊盘的表面上的第一和第二开口中的导电元件。 本结构有助于加强导电元件与相应的电连接焊盘之间的接合。

公开(公告)号：US08218333B2

公开(公告)日：2012-07-10

申请号：US12401247

申请日：2009-03-10

Applicant: Masato Udaka ,  Seiji Tokii

Inventor： Masato Udaka ,  Seiji Tokii

IPC: H05K1/18

CPC classification number: H05K3/3436 ,  H01R12/523 ,  H05K1/113 ,  H05K2201/09381 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09572 ,  Y02P70/613 ,  Y10T29/49213

Abstract: The present invention provides a printed circuit board capable of sufficiently ensuring joint strength and joint reliability when mounting a surface mounted device, and a mounting structure for a surface mounted device using the printed circuit board. A BGA package as a surface mounted device includes a plurality of solder balls arranged thereon and a printed circuit board includes a plurality of mounting pads corresponding respectively to the plurality of solder balls. The BGA package is connected to the mounting pads on the printed circuit board due to melting of the solder balls, thereby mounted on the printed circuit board. A concave via hole is formed on each of the mounting pads having a circular surface shape and a part of the solder ball is in the convex via hole. Here, the center of the convex via hole is apart from the center of each of the mounting pads by at least the diameter of the concave via hole.

Abstract translation: 本发明提供了一种印刷电路板，其能够在安装表面安装装置时足以确保接合强度和接头可靠性，以及使用印刷电路板的表面安装装置的安装结构。 作为表面安装器件的BGA封装包括布置在其上的多个焊球，并且印刷电路板包括分别对应于多个焊球的多个安装焊盘。 BGA封装由于焊球的熔化而连接到印刷电路板上的安装焊盘，从而安装在印刷电路板上。 在具有圆形表面形状的每个安装焊盘上形成凹通孔，并且焊球的一部分在凸通孔中。 这里，凸通孔的中心至少与凹通孔的直径相距离每个安装焊盘的中心。

公开(公告)号：US20120060368A1

公开(公告)日：2012-03-15

申请号：US13301812

申请日：2011-11-22

Applicant: Cheng-Po Yu ,  Han-Pei Huang

Inventor： Cheng-Po Yu ,  Han-Pei Huang

IPC: H05K3/22

CPC classification number: H05K1/11 ,  H05K1/0284 ,  H05K1/142 ,  H05K3/185 ,  H05K3/4007 ,  H05K3/4661 ,  H05K2201/0236 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09163 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09845 ,  H05K2203/1327 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T428/24802 ,  Y10T428/24917

Abstract: A method of fabrication a circuit board structure comprising providing a circuit board main body, forming a molded, irregular plastic body having a non-plate type, stereo structure and at least one scraggy surface by encapsulating at least a portion of said circuit board main body with injection molded material, and forming a first three-dimensional circuit pattern on said molded, irregular plastic body thereby defining a three-dimensional circuit device.

Abstract translation: 一种制造电路板结构的方法，包括提供电路板主体，通过封装所述电路板主体的至少一部分来形成具有非板型，立体结构和至少一个刮痕表面的模制的不规则塑料体 并且在所述模制的不规则塑料体上形成第一三维电路图案，从而限定三维电路装置。