-
公开(公告)号：SG11202012334SA
公开(公告)日：2021-06-29
申请号：SG11202012334S
申请日：2019-11-21
Inventor： YANG YAN , LI ZHIHUA , WANG WENWU
IPC: H01L31/0203
Abstract: An integrated method for a silicon optical adapter adapter plate and a three-dimensional architecture, capable of making the chip encapsulation area smaller, and achieving a higher integration level, a smaller electrical signal delay and a higher bandwidth and speed, and an integrated method for a surface electrode ion trap, a silicon optical device and a three-dimensional architecture, an integrated structure and a three-dimensional architecture with a strong stability, miniaturization, versatility and expandability. The integration of the three-dimensional architecture is realized on the basis of the integration of a through-silicon via and a silicon optical device, so that the integrated chip area can be smaller and the integration level can be higher, and the formed three-dimensional architecture has a smaller electrical signal delay and a higher bandwidth and speed. The surface electrode ion trap is integrated with a silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector, a silicon grating and/or a silicon nitride grating and a through-silicon via. After being powered on, the surface electrode ion trap is used to capture ions and trap same in a certain range. A laser source is coupled to the silicon grating and/or the silicon nitride grating by using any coupling mode such as end-face coupling. The laser is emitted to the ions via the silicon grating and/or the silicon nitride grating on three orientations to complete addressing. The ions can undergo energy level transition after being excited by light. After energy level transition, the ions can radiate fluorescent light. The fluorescent light is detected by the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector, and the detection of quantum bit information is finally completed.
-
公开(公告)号：US12287454B2
公开(公告)日：2025-04-29
申请号：US17310206
申请日：2019-02-01
Inventor： Lina Shi , Longjie Li , Kaiping Zhang , Jiebin Niu , Changqing Xie , Ming Liu
Abstract: The present disclosure provides a method for fabricating an anti-reflective layer on a quartz surface by using a metal-induced self-masking etching technique, comprising: performing reactive ion etching to a metal material and a quartz substrate by using a mixed gas containing a fluorine-based gas, wherein metal atoms and/or ions of the metal material are sputtered to a surface of the quartz substrate, to form a non-volatile metal fluoride on the surface of the quartz substrate; forming a micromask by a product of etching generated by reactive ion etching gathering around the non-volatile metal fluoride; and etching the micromask and the quartz substrate simultaneously, to form an anti-reflective layer having a sub-wavelength structure.
-
公开(公告)号：US12278104B2
公开(公告)日：2025-04-15
申请号：US17928951
申请日：2021-09-09
Inventor： Fengwen Mu , Xinhua Wang , Sen Huang , Ke Wei , Xinyu Liu
IPC: H01L21/24 , H01L21/02 , H01L23/373
Abstract: The present disclosure relates to the technical field of semiconductors. Disclosed is a multi-layer semiconductor material structure and a preparation method thereof, solving the problems of the existing semiconductor materials that have poor heat dissipation, high cost, and cannot be mass-produced. The multi-layer semiconductor material structure includes a highly thermally conductive support substrate and a crystallized device function layer, where the device function layer is provided on the highly thermally conductive support substrate, and has a single-crystal surface layer.
-
14.发明授权公开(公告)号：US12274069B2
公开(公告)日：2025-04-08
申请号：US17783627
申请日：2021-12-23
Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY , INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
Inventor： Weixing Huang , Huilong Zhu
Abstract: A semiconductor device, including a substrate, a first electrode layer, a functional layer, and a second electrode layer. The functional layer is located between the first electrode layer and the second electrode layer, and includes a first region and a second region having a C-shaped structure surrounding the first region. The C-shape structure opens toward a direction that is parallel with the substrate and away from the first region, that is, the C-shaped structure opens toward a distal side. The first region is made of at least germanium, and the second region includes a C-shaped ferroelectric layer and a C-shaped gate that are sequentially stacked. The C-shaped ferroelectric layer serves as a memory layer of the memory device.
-
公开(公告)号：US12260902B2
公开(公告)日：2025-03-25
申请号：US18042574
申请日：2020-08-24
Inventor： Qing Luo , Bing Chen , Hangbing Lv , Ming Liu , Cheng Lu
IPC: G11C7/22 , G11C11/408 , G11C11/4094 , G11C11/4096 , H03K19/017
Abstract: A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.
-
Patent Agency Ranking
公开(公告)号：US20250081530A1
公开(公告)日：2025-03-06
申请号：US18725967
申请日：2023-11-27
Inventor： Junjie LI , Enxu LIU , Na ZHOU , Jianfeng GAO , Junfeng LI , Yongliang LI , Jun LUO , Wenwu WANG
IPC: H01L29/423 , H01L21/3065 , H01L21/762 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/66 , H01L29/775 , H01L29/786
Abstract: A semiconductor device and a method for manufacturing the same. The method comprises: providing a substrate; forming a fin, a dummy gate, a first spacer, and a hard mask on a surface of the substrate; etching the substrate to form a groove located directly beneath the fin and running through a second spacer; forming, in the groove, a filling layer made of an insulating dielectric material, and thermal conductivity of the insulating dielectric material is higher than that of the substrate; removing the second spacer through etching; removing two opposite ends of each sacrificial layer to form cavities; filling the cavities to form inner spacers; forming a source and a drain on the substrate; forming a first dielectric layer; planarizing the first dielectric layer to expose the dummy gate; removing the dummy gate to release a channel comprising conductive nanosheets; forming a surrounding gate surrounding the conductive nanosheets.
-
17.发明申请公开(公告)号：US20250056850A1
公开(公告)日：2025-02-13
申请号：US18719156
申请日：2022-02-17
Inventor： Huilong ZHU
IPC: H01L29/06 , H01L21/762 , H01L21/8234 , H01L27/088 , H01L29/08 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
Abstract: A nanowire/nanosheet device with a crystal spacer, a method of manufacturing the nanowire/nanosheet device with the crystal spacer, and an electronic apparatus including the nanowire/nanosheet device are provided. The nanowire/nanosheet device includes: a substrate; a nanowire/nanosheet spaced apart from a surface of the substrate and extending in a first direction; source/drain layers located at opposite ends of the nanowire/nanosheet in the first direction and adjoining the nanowire/nanosheet; a gate stack extending in a second direction intersecting with the first direction to surround the nanowire/nanosheet; and a spacer provided on a sidewall of the gate stack, wherein the spacer has a crystal structure substantially identical to a crystal structure of the nanowire/nanosheet in at least a part of a region of the spacer adjacent to the nanowire/nanosheet.
-
公开(公告)号：US20250006822A1
公开(公告)日：2025-01-02
申请号：US18708028
申请日：2023-11-27
Inventor： Na Zhou , Junjie Li , Jianfeng Gao , Tao Yang , Junfeng Li , Jun Luo
IPC: H01L29/66 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/786
Abstract: A method for manufacturing a gate-all-around TFET device. The method comprises: forming, on a substrate, a channel stack comprising channel layer(s) and sacrificial layer(s) that alternate with each other; forming, on the substrate, a dummy gate astride the channel stack; forming a first spacer at a surface of the dummy gate; etching the sacrificial layer(s) to form recesses on side surfaces of the channel stack; forming second spacers in the recesses, respectively; fabricating a source and a drain separately, where a region for fabricating the source is shielded by a dielectric material when fabricating the drain, and a region for fabricating the drain is shielded by another dielectric material when fabricating the source; etching the dummy gate and the sacrificial layer(s) to form a space for a surrounding gate; and fabricating a surrounding dielectric-metal gate in the space.
-
公开(公告)号：US20240421032A1
公开(公告)日：2024-12-19
申请号：US18703924
申请日：2021-11-02
Inventor： Gang ZHANG , Chunlong LI , Zongliang HUO , Tianchun YE
Abstract: The memory cell includes: an array of channel layers including N channel layers vertically provided on a substrate, a tunneling layer and a memory layer being sequentially provided on an outer side of the channel layers; N thermal conductive cores provided in the N channel layers respectively and penetrating the substrate; and an array of thermocouples including a thermocouple word line layer grown on the substrate and N thermocouple layers on the thermocouple word line layer, the thermocouple layers being connected one-to-one with the thermal conductive cores. A first potential difference is applied between the thermocouple word line layer and the thermocouple layer, and the thermal conductive core connected with the thermocouple layer is heated, so that the channel layer and the memory layer corresponding to the thermal conductive core are maintained at first and second preset temperatures respectively under a thermal insulation effect of the tunneling layer.
-
20.发明公开公开(公告)号：US20240365534A1
公开(公告)日：2024-10-31
申请号：US18630435
申请日：2024-04-09
Inventor： Huilong ZHU , Tianchun YE , Jun LUO
CPC classification number: H10B12/482 , H10B12/05 , H10B12/485 , H10B12/488 , H10B61/22 , H10N50/10
Abstract: A memory device, including: device layers vertically stacked on a substrate, each device layer including an array of active regions of selection transistors, the array including rows in a first direction and columns in a second direction, the active region including a lower source/drain region, a channel portion, and an upper source/drain region; bit lines arranged in the second direction and extending in the first direction along rows; word line layers vertically stacked and corresponding to the device layers, and each including word lines arranged in the first direction and extending in the second direction to at least partially surround a channel portion in a column of a device layer; sub bit lines extending vertically from each bit line and each electrically connected to a lower source/drain region in a row in each device layer above the bit line; and a memory element electrically connected to the upper source/drain region.
-
-
-
-
-
-
-
-
-
Search Results
761
records
(took 0.039 seconds)
