公开(公告)号：WO0077832A3

公开(公告)日：2001-09-07

申请号：PCT/US0015956

申请日：2000-06-09

Applicant: SYMETRIX CORP ,  MATSUSHITA ELECTRONICS CORP

Inventor： HAYASHI SHINICHIRO ,  JOSHI VIKRAM ,  SOLAYAPPAN NARAYAN ,  CUCHIARO JOSEPH D ,  PAZ DE ARAUJO CARLOS A

IPC: C01G35/00 ,  G11C11/22 ,  H01L21/314 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/06 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: G11C11/22 ,  G11C11/223 ,  H01L21/31691 ,  H01L27/0629 ,  H01L29/78391

Abstract: A high dielectric constant insulator including a thin film of a metal oxide selected from the group consisting of tungsten-bronze-type oxides, pyrochlore-type oxides, and combinations of Bi2O3 with an oxide selected from the group consisting of perovskites and pyrochlore-type oxides. An embodiment contains metal oxides represented by the general stoichiometric formulae AB2O6, A2B2O7 and A2Bi2B2O10, wherein A represents A-site atoms selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, K, Na and La; and B represents B-site atoms selected from the group of metals consisting of Ti, Zr, Ta, Hf, Mo, W and Nb. Preferably, the metal oxides are (BaxSr1-x)(TayNb1-y)2O6,where 0 /=40, and preferably about 100. The value of Vcc in the metal oxides of the invention is close to zero. The value of Tcc is

Abstract translation: 一种高介电常数绝缘体，包括选自钨青铜型氧化物，烧绿石型氧化物和Bi 2 O 3与选自钙钛矿和烧绿石型氧化物的氧化物的组合的金属氧化物的薄膜 。 一个实施方案包含由一般化学计量式AB2O6，A2B2O7和A2B2B2O10表示的金属氧化物，其中A表示选自由Ba，Bi，Sr，Pb，Ca，K，Na和La组成的金属组中的A位原子; B表示选自由Ti，Zr，Ta，Hf，Mo，W和Nb组成的金属组中的B位原子。 优选地，金属氧化物是（BaxSr1-x）（TayNb1-y）2O6，其中0≤x≤1.0且0≤y≤1.0; （BaxSr1-x）2（TayNb1-y）2O7，其中0≤x≤1.0且0≤y≤1.0; 和（BaxSr1-x）2Bi2（TayNb1-y）2O10，其中0≤x≤1.0且0≤y≤1.0。 根据本发明的薄膜的相对介电常数≥40，优选约为100.本发明金属氧化物中的Vcc值接近零。 Tcc的值<1000ppm，优选<100。

公开(公告)号：WO0068472A8

公开(公告)日：2001-04-19

申请号：PCT/US0009998

申请日：2000-04-13

Applicant: CBL TECHNOLOGIES INC ,  MATSUSHITA ELECTRONICS CORP

Inventor： SOLOMON GLENN S ,  MILLER DAVID J ,  UEDA TETSUZO

IPC: C23C16/44 ,  C23C16/455 ,  C23C16/458 ,  C23C16/52 ,  C30B25/12 ,  H01L21/205 ,  C30B25/02 ,  C30B25/14 ,  C30B25/16

CPC classification number: C23C16/4582 ,  C23C16/45591 ,  C30B25/12

Abstract: A vapor-phase deposition system includes one or more channel units for promoting the downstream passage of reagent gases. A reactor (21) of a vapor-phase deposition system may include one or more channels (25) to promote passage of reagent gases (5) beneath a susceptor stage (33). A susceptor, for arrangement within a reactor during epitaxial growth on a substrate, may include a truncated side (35). The substrate may be aligned with a lower edge of the truncated side, thereby, avoiding chemical deposition on surfaces upstream of the substrate. One or more channels of the susceptor promote the downstream passage of reagent gases within the reactor. Methods for vapor-phase deposition and for promoting downstream passage of reagent gases within a reactor are also disclosed.

Abstract translation: 气相沉积系统包括用于促进反应气体的下游通过的一个或多个通道单元。 气相沉积系统的反应器（21）可以包括一个或多个通道（25），以促进基座台（33）下面的试剂气体（5）的通过。 用于在衬底外延生长期间在反应器内布置的感受体可以包括截顶侧（35）。 衬底可以与截顶侧的下边缘对准，从而避免在衬底上游的表面上的化学沉积。 基座的一个或多个通道促进反应器内的试剂气体的下游通过。 还公开了用于气相沉积和促进反应器内的试剂气体的下游通过的方法。

公开(公告)号：WO9734320A9

公开(公告)日：1999-12-16

申请号：PCT/US9704185

申请日：1997-03-14

Applicant: SYMETRIX CORP ,  MATSUSHITA ELECTRONICS CORP

Inventor： MCMILLAN LARRY D ,  SCOTT MICHAEL C ,  PAZ DE ARAUJO CARLOS A ,  OTSUKI TATSUO ,  HAYASHI SHINICHIRO

IPC: B05D1/00 ,  B05D3/04 ,  B05D7/24 ,  C23C16/44 ,  C23C16/448 ,  C23C16/455 ,  C23C16/46 ,  C23C16/48 ,  C23C16/52 ,  C23C18/12 ,  C23C18/14 ,  C23C26/02 ,  C30B7/00 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L27/115 ,  H01L41/24 ,  H05K3/10

CPC classification number: H01L21/316 ,  B05D1/00 ,  B05D1/60 ,  B05D3/0493 ,  C23C16/4412 ,  C23C16/4486 ,  C23C16/45561 ,  C23C16/4558 ,  C23C16/46 ,  C23C16/482 ,  C23C16/52 ,  C23C18/1212 ,  C23C18/1287 ,  C23C18/14 ,  C23C26/02 ,  C30B7/00 ,  C30B29/68 ,  H01L21/314 ,  H01L21/31691 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60 ,  H01L41/316 ,  H05K3/105

Abstract: A precursor liquid (64) comprising silicon in a xylene solvent is prepared, a substrate (5, 71) is placed within a vacuum deposition chamber (2), the precursor liquid is misted, and the mist (66) is flowed into the deposition chamber while maintaining the chamber at ambient temperature to deposit a layer of the precursor liquid on the substrate. The liquid is dried, baked, and annealed to form a thin film (1224, 77) of silicon dioxide or silicon glass on the substrate. Then an integrated circuit (100) is completed to include at least a portion of the silicon dioxide or silicon glass layer as an insulator (77) for an electronic device (76) in the integrated circuit.

Abstract translation: 制备在二甲苯溶剂中含硅的前体液体（64），在真空沉积室（2）内放置基材（5,71），使前体液体雾化，并将雾（66）流入沉积物 同时将室保持在环境温度下，以将一层前体液体沉积在基底上。 将液体干燥，烘烤和退火，以在基底上形成二氧化硅或硅玻璃的薄膜（1224,77）。 然后完成集成电路（100），以将至少一部分二氧化硅或硅玻璃层作为用于集成电路中的电子器件（76）的绝缘体（77）。

公开(公告)号：WO0109930A3

公开(公告)日：2001-07-05

申请号：PCT/US0040344

申请日：2000-07-11

Applicant: SYMETRIX CORP ,  MATSUSHITA ELECTRONICS CORP

Inventor： MCMILLAN LARRY D ,  PAZ DE ARAUJO CARLOS A ,  ARITA KOJI ,  AZUMA MASAMICHI

IPC: H01L21/02 ,  H01L21/82 ,  H01L29/12 ,  H01L29/92

CPC classification number: C23C18/1216 ,  C23C18/1245 ,  C23C18/1279 ,  C23C18/1283 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

Abstract: An integrated circuit capacitor (10, 25, 30, 402) containing a thin film of dielectric metaloxide (20, 420) is formed above a silicon germanium substrate (12, 406). A silicon nitride diffusion barrier layer (24, 324, 414) is deposited on a silicon germanium substrate to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer is deposited on the diffusion barrier layer. A bottom electrode (16, 418) is formed on the stress reduction layer, then a liquid precursor is spun on the bottom electrode, dried at about 400 DEG C, and annealed at between 600 DEG C and 850 DEG C to form a BST capacitor dielectric (20, 420). A top electrode (22, 422) is deposited on the dielectric and annealed. The integrated circuit may also include a BiCMOS device, a HBT device or a MOSFET.

Abstract translation: 在硅锗基板（12,406）的上方形成包含介电金属氧化物（20,420）的薄膜的集成电路电容器（10,25,30,402）。 氮化硅扩散阻挡层（24,324,414）沉积在硅锗衬底上以防止随后的加热步骤中衬底的蒸发。 二氧化硅应力降低层沉积在扩散阻挡层上。 在应力降低层上形成底部电极（16,418），然后在底部电极上旋转液体前体，在约400℃下干燥，并在600℃和850℃之间退火以形成BST电容器 电介质（20,420）。 顶部电极（22,422）沉积在电介质上并退火。 集成电路还可以包括BiCMOS器件，HBT器件或MOSFET。

公开(公告)号：WO0156065A3

公开(公告)日：2001-12-27

申请号：PCT/JP0100466

申请日：2001-01-24

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： NASU TORU ,  ARITA KOJI

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/51

CPC classification number: H01L21/02197 ,  H01L21/02282 ,  H01L21/31691 ,  H01L28/55 ,  H01L29/516

Abstract: A coating of liquid precursor for forming a layered superlattice material is applied to a substrate, the substrate is dried and then pretreated using RTP at 450 DEG C for 5 minutes. Following the RTP, the substrate is annealed in an unreactive gas at a temperature not exceeding 800 DEG C, then annealed in oxygen gas at a temperature not exceeding 800 DEG C for one hour to form a thin film (124, 422) of layered superlattice material.

Abstract translation: 将用于形成层状超晶格材料的液体前体涂层施加到基底上，将基底干燥，然后使用RTP在450℃预处理5分钟。 在RTP之后，将衬底在不超过800℃的温度下在非活性气体中退火，然后在不超过800℃的温度下在氧气中退火1小时，以形成层状超晶格的薄膜（124,422） 材料。

公开(公告)号：WO9965051A3

公开(公告)日：2000-03-16

申请号：PCT/US9912717

申请日：1999-06-07

Applicant: SYMETRIX CORP ,  MATSUSHITA ELECTRONICS CORP

Inventor： KANO GOTA ,  SHIMADA YASUHIRO ,  HAYASHI SHINICHIRO ,  ARITA KOJI ,  PAZ DE ARAUJO CARLOS A ,  CUCHIARO JOSEPH D ,  MCMILLAN LARRY D

IPC: G02F1/136 ,  G02F1/13357 ,  G09F9/30 ,  H01J9/02 ,  H01J29/04 ,  H01J31/12 ,  H01J1/30

CPC classification number: G02F1/133603

Abstract: A thin film of ferroelectric layered superlattice material in a flat panel display device is energized to selectively influence the display image. In one embodiment, a voltage pulse causes the layered superlattice material to emit electrons that impinge upon a phosphor, causing the phosphor to emit light. In another embodiment, an electric potential creates a remanent polarization in the layered superlattice material, which exerts an electric field in liquid crystal layer, thereby influencing the transmissivity of light through the liquid crystal. The layered superlattice material is a metal oxide formed using an inventive liquid precursor containing an alkoxycarbolyxate. The thin film thickness is preferably in the range of 50-140 nm, so that polarizability and transparency of the thin film is enhanced. A display element may comprise a varistor device to prevent cross-talk between pixels and to enable sudden polarization switching. A functional gradient in the ferroelectric thin film enhances electron emission. Two ferroelectric elements, one on either side of the phosphor may be used to enhance luminescence. A phosphor can be sandwiched between a dielectric and a ferroelectric layer to enhance emission.

Abstract translation: 平板显示装置中的铁电层状超晶格材料薄膜被通电以选择性地影响显示图像。 在一个实施例中，电压脉冲使得层状超晶格材料发射撞击磷光体的电子，导致磷光体发光。 在另一个实施例中，电位在层状超晶格材料中产生剩余极化，其在液晶层中施加电场，从而影响透过液晶的透射率。 层状超晶格材料是使用本发明的含有烷氧基羧酸的液体前体形成的金属氧化物。 薄膜厚度优选在50-140nm的范围内，从而提高了薄膜的极化率和透明度。 显示元件可以包括用于防止像素之间的串扰并允许突发极化切换的变阻器装置。 铁电薄膜中的功能梯度增强了电子发射。 可以使用两个铁电元件，一个在荧光体的两侧，以增强发光。 磷光体可以夹在电介质和铁电层之间以增强发射。

公开(公告)号：WO9900826A3

公开(公告)日：1999-05-27

申请号：PCT/JP9802544

申请日：1998-06-08

Applicant: MATSUSHITA ELECTRONICS CORP ,  MINAMIO MASANORI ,  KONISHI SATORU ,  MORISHITA YOSHIHIKO ,  YAMADA YUICHIRO ,  ITOH FUMITO

Inventor： MINAMIO MASANORI ,  KONISHI SATORU ,  MORISHITA YOSHIHIKO ,  YAMADA YUICHIRO ,  ITOH FUMITO

IPC: H01L23/28 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50

CPC classification number: H01L23/49541 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead portions (13) of the lead frame (9); and a sealing resin (15), and the lead frame (9) is subjected to an upsetting process so that a supporting portion (11) is located at a position higher than the inner lead portions (13). Since the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the supporting portion, the adhesiveness between the lead frame and the sealing resin can be improved, and high reliability and thinning are realized. Since at least one groove portion is disposed in the surface of each of the inner lead portions (13), the anchoring effect to the sealing resin (15), stress acting on a lead portion of a product, and stress to the thin metal wires (14) can be relaxed, and leads and the thin metal wires can be prevented from peeling off.

Abstract translation: 一种树脂模制型半导体器件具有：安装在引线框（9）的芯片焊盘部分（11）上的半导体芯片（12）; 将半导体芯片12的端子与引线框9的内引线部13连接的细金属线14; 和密封树脂（15），并且引线框架（9）经受镦粗处理，使得支撑部分（11）位于比内引线部分（13）更高的位置处。 由于在支撑部的下方存在与镦锻的台阶差对应的厚度的密封树脂，所以能够提高引线框与密封树脂的密合性，实现高可靠性和薄型化。 由于在各内引线部（13）的表面配置有至少一个槽部，因此对密封树脂（15）的固定作用，作用于产品的引线部的应力以及对金属细线 （14）可以松弛，并且引线和细金属线可以防止剥落。

公开(公告)号：US6271070B2

公开(公告)日：2001-08-07

申请号：US20656198

申请日：1998-12-08

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： KOTANI NAOKI ,  SHIMIZU KEIICHIRO

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8249 ,  H01L21/8238

CPC classification number: H01L21/763 ,  H01L21/76202 ,  H01L21/8249

Abstract: On a main surface of a p-type silicon substrate having a bipolar transistor forming region and a MOS transistor forming region, an epitaxial layer is grown and n-type buried layers are formed. After forming a trench penetrating the buried layer, a buried polysilicon layer is formed in the trench. Then, a threshold control layer, a punch-through stopper layer, a channel stopper layer, an n-type well layer and a p-type well layer of each MOSFET are formed. At this point, since the well layer is formed through high energy ion implantation, the n-type buried layer is suppressed from being enlarged, and hence, time required for forming the trench can be shortened. Thus, a practical method of manufacturing a semiconductor device is provided.

Abstract translation: 在具有双极晶体管形成区域和MOS晶体管形成区域的p型硅衬底的主表面上，生长外延层并形成n型掩埋层。 在形成穿透掩埋层的沟槽之后，在沟槽中形成掩埋多晶硅层。 然后，形成每个MOSFET的阈值控制层，穿通停止层，沟道阻挡层，n型阱层和p型阱层。 此时，由于通过高能离子注入形成了阱层，因此能够抑制n型掩埋层的扩大，能够缩短形成沟槽所需的时间。 因此，提供了制造半导体器件的实用方法。

公开(公告)号：US3922710A

公开(公告)日：1975-11-25

申请号：US46631974

申请日：1974-05-02

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： KOIKE SUSUMU

IPC: G11C16/04 ,  H01L23/29 ,  H01L29/00 ,  H01L29/792 ,  H03K3/26 ,  H03K3/356 ,  H01L29/88 ,  H01L29/34 ,  H01L29/78 ,  H01L29/90

CPC classification number: H03K3/356008 ,  G11C16/0466 ,  H01L23/291 ,  H01L24/06 ,  H01L29/00 ,  H01L29/792 ,  H01L2924/12036 ,  H01L2924/1306 ,  H03K3/26 ,  H03K3/356 ,  Y10S148/114 ,  H01L2924/00

Abstract: A first thin insulating film capable of being pierced or punched through by carriers such as an SiO2 film 20 A thick is deposited on the surface of a P-type silicon substrate and a second insulating film with a trap level such as an Si3N4 film 500 to 600 A thick is laid on the first insulating film. Upon application of an electric field through a metal electrode mounted on the second insulating film to the combination of the insulating films, electrons captured at the trap level of the second insulating film transfer through the first insulating film to the surface of the substrate thereby forming an inversion layer. When the inversion layer is connected with the two junction regions formed in the surface of the substrate, the reverse current level of the junction region increases semipermanently due to the breakdown voltage of the junction until the inversion layer is cancelled by the application of a reverse electric field. This principle is used to produce a memory device characterized by an exact operation comprising a semiconductor, the first thin insulating film, the second insulating film with a trap level, the second insulating film, the metal electrode and two PN junctions which have different junction breakdown voltages.

Abstract translation: 能够通过诸如SiO 2膜厚度为20A的载体刺穿或穿孔的第一薄薄绝缘膜沉积在P型硅衬底的表面和具有陷阱水平的第二绝缘膜，例如Si 3 N 4膜500至 第一绝缘膜上放置厚度为600。 当通过安装在第二绝缘膜上的金属电极施加电场到绝缘膜的组合时，在第二绝缘膜的陷阱电平处捕获的电子通过第一绝缘膜转移到基板的表面，从而形成 逆温层。 当反型层与形成在衬底的表面中的两个结区连接时，结区的反向电流水平由于结的击穿电压而长时间增加，直到通过施加反向电 领域。 该原理用于制造存储器件，其特征在于精确的操作，其包括半导体，第一薄绝缘膜，具有陷阱级的第二绝缘膜，第二绝缘膜，金属电极和具有不同结断层的两个PN结 电压。

公开(公告)号：US3910662A

公开(公告)日：1975-10-07

申请号：US40853473

申请日：1973-10-23

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： FUJIO HINOMARU ,  FUKUNAGA KAZUNORI ,  NAKAMURA NAOYUKI

IPC: H01J9/24 ,  H01J9/46 ,  H01J9/38

CPC classification number: H01J9/46

Abstract: An apparatus for producing fluorescent lamps comprises an intermittently rotatable turret having a plurality of glass tube supporting arms extending radially from the turret. The apparatus is so arranged that a plurality of glass tubes supported from the supporting arms are simultaneously subjected to working operations such as heating, bending, evacuation, filling, sealing etc. at a plurality of stations in each of which a plurality of glass tubes are subjected to the same working operation to improve the productivity of the apparatus.

Abstract translation: 一种用于生产荧光灯的设备包括间歇旋转的转盘，其具有从转台径向延伸的多个玻璃管支撑臂。 该装置被布置成使得从支撑臂支撑的多个玻璃管同时经受多个工位的加热，弯曲，抽空，填充，密封等工作，其中多个玻璃管是 经受相同的工作操作以提高设备的生产率。