公开(公告)号：KR1020110108216A

公开(公告)日：2011-10-05

申请号：KR1020100055098

申请日：2010-06-10

Applicant: 삼성전자주식회사

Inventor： 황완식 ,  나카니시토시로 ,  유동철 ,  황기현 ,  최한메 ,  박찬진

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: 3차원 반도체 장치가 제공된다. 이 장치는 반도체 기판 상에 차례로 적층된 선택 구조체 및 메모리 구조체를 포함한다. 선택 구조체는 선택 라인들, 이들을 관통하여 반도체기판에 접촉하는 선택 활성 패턴, 그리고 선택 라인들과 선택 활성 패턴 사이에 배치되는 선택 게이트 절연막을 포함하고, 메모리 구조체는 워드 라인들, 이들을 관통하여 선택 활성 패턴에 접촉하는 메모리 활성 패턴, 그리고 워드라인들과 메모리 활성 패턴 사이에 배치되는 메모리 게이트 절연막을 포함한다. 이때, 메모리 게이트 절연막의 일부는 연장되어 워드라인의 상부면 및 하부면을 덮는다.

公开(公告)号：KR1020140025864A

公开(公告)日：2014-03-05

申请号：KR1020120092170

申请日：2012-08-23

Applicant: 삼성전자주식회사

Inventor： 이성해 ,  나카니시토시로 ,  김동우 ,  김재호

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L29/7926 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66833 ,  H01L21/823487

Abstract: In a vertical type semiconductor device and a method of manufacturing the same, the vertical type semiconductor device includes a filler structure which protrudes from the upper surface of a substrate and includes a semiconductor pattern and a channel pattern. First word line structures which are extended in a horizontal direction, surround the filler structure and faces the channel pattern that is formed. Second word line structures which are extended in a horizontal direction, surround the filler structure, and includes one surface which faces the semiconductor pattern and the other surface which faces the substrate surface part are formed. An impurity region for threshold voltage control is formed under a semiconductor pattern surface facing the second word line structure. A common source line is formed on a surface part which is adjacent to the end part of the sidewall of the second word line structures. The vertical type semiconductor device with good threshold voltage distribution can be fabricated by a simple process. [Reference numerals] (AA) First direction; (BB) Second direction; (CC) Third direction

Abstract translation: 在垂直型半导体器件及其制造方法中，垂直型半导体器件包括从衬底的上表面突出并包括半导体图案和沟道图案的填充结构。 在水平方向上延伸的第一字线结构，围绕填充物结构并面向所形成的沟道图案。 在水平方向上延伸的第二字线结构，围绕填料结构，并且包括面对半导体图案的一个表面和面向衬底表面部分的另一个表面。 用于阈值电压控制的杂质区域形成在面对第二字线结构的半导体图形表面下。 在与第二字线结构的侧壁的端部相邻的表面部分上形成共同的源极线。 具有良好阈值电压分布的垂直型半导体器件可以通过简单的工艺制造。 （附图标记）（AA）第一方向; （BB）第二方向; （CC）第三方向

公开(公告)号：KR1020140011872A

公开(公告)日：2014-01-29

申请号：KR1020120079541

申请日：2012-07-20

Applicant: 삼성전자주식회사

Inventor： 김비오 ,  나카니시토시로 ,  노진태 ,  선창우 ,  임승현 ,  안재영 ,  황기현

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L29/66666 ,  H01L21/8239 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H01L21/823885

Abstract: In a method for manufacturing a vertical memory device, sacrificial layers and insulating layers are formed on a substrate. The sacrificial layers and the insulating layers are partially etched to form an opening part for exposing the surface of a substrate. A charge trapping layer and a tunnel insulating layer are formed in the sidewall of the opening part. A channel layer including N-type-impurity-doped polysilicon is formed along the inner wall profile of the opening part on the tunnel insulating layer. A burying insulating pattern is formed at the opening part formed in the channel layer. Also, a blocking dielectric layer and a control gate are formed on the charge trapping layer of one sidewall of the channel layer.

Abstract translation: 在垂直存储器件的制造方法中，在衬底上形成牺牲层和绝缘层。 牺牲层和绝缘层被部分蚀刻以形成用于暴露衬底表面的开口部分。 电荷捕获层和隧道绝缘层形成在开口部分的侧壁中。 沿着隧道绝缘层上的开口部分的内壁轮廓形成包括N型杂质掺杂多晶硅的沟道层。 在形成于通道层中的开口部分形成埋入绝缘图案。 此外，在沟道层的一个侧壁的电荷捕获层上形成阻挡介质层和控制栅极。

公开(公告)号：KR1020100111165A

公开(公告)日：2010-10-14

申请号：KR1020090029590

申请日：2009-04-06

Applicant: 삼성전자주식회사

Inventor： 나카니시토시로 ,  한정희 ,  채수두

IPC: H01L21/8229

CPC classification number: H01L27/1021 ,  G11C13/0004 ,  G11C2213/71 ,  H01L27/101

Abstract: PURPOSE: A 3D memory device is provided so that the manufacturing cost can be reduced in comparison with the other 3D memory device formed into the multilayer. CONSTITUTION: A 3D memory device comprises the semiconductor substrate(100), the insulating layer(150) between the plane word line(160) and the gate, activity post(180), and information storage film(170) is included. The semiconductor substrate comprises the common source area. The insulating layer is by turns laminated between plane word lines and gate on the semiconductor substrate.

Abstract translation: 目的：提供3D存储器件，以便与形成为多层的其它3D存储器件相比，可以减少制造成本。 构成：包括半导体衬底（100），平面字线（160）和栅极之间的绝缘层（150），活动柱（180）和信息存储膜（170）的3D存储器件。 半导体衬底包括公共源极区域。 绝缘层依次层叠在半导体衬底上的平面字线和栅极之间。

公开(公告)号：KR1020100095263A

公开(公告)日：2010-08-30

申请号：KR1020090014449

申请日：2009-02-20

Applicant: 삼성전자주식회사

Inventor： 나카니시토시로 ,  박찬진 ,  최시영 ,  구본영

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/11565 ,  H01L21/31051 ,  H01L21/76224

Abstract: PURPOSE: A nonvolatile memory device and a forming method thereof are provided to improve the reliability of a nonvolatile memory device by preventing a charge trap layer trapped on a first region from being moved to a second region. CONSTITUTION: A device isolation pattern(120) defines an active region(110) on a semiconductor substrate and is extended in a first direction. A charge trap layer(140) covers the active region and a device isolation pattern. A word line(160) is extended in a second direction cross the active region of the charge trap layer.

Abstract translation: 目的：提供一种非易失性存储器件及其形成方法，用于通过防止捕获在第一区域上的电荷陷阱层移动到第二区域来提高非易失性存储器件的可靠性。 构成：器件隔离图案（120）在半导体衬底上限定有源区（110）并沿第一方向延伸。 电荷陷阱层（140）覆盖有源区域和器件隔离图案。 字线（160）在与电荷陷阱层的有源区域交叉的第二方向上延伸。