公开(公告)号：KR1020150108986A

公开(公告)日：2015-10-01

申请号：KR1020140031695

申请日：2014-03-18

Applicant: 삼성전자주식회사

Inventor： 최승필 ,  유형우 ,  신나래 ,  김기준 ,  김용훈 ,  박수진 ,  서명식 ,  이재범 ,  장은종

IPC: H01L23/12 ,  H01L23/48

CPC classification number: H01L23/50 ,  G09G5/005 ,  G09G2300/0404 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2340/0435 ,  H01L23/49822 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/08 ,  H01L2224/04105 ,  H01L2224/06153 ,  H01L2224/08237

Abstract: 본발명의칩 온필름패키지는제 1 장변을따라배치되는하나이상의기본출력패드및 제 1 장변과마주보는제 2 장변을따라배치되는하나이상의확장출력패드를포함하는집적회로칩을포함한다. 나아가, 본발명의칩 온필름패키지는하부덮개, 각각의사이에간격을두고하부덮개의일면위에배치되는복수의필름도선, 및하부덮개의일면위에서복수의필름도선을덮는상부덮개를포함하는필름을포함한다. 하나이상의기본출력패드및 하나이상의확장출력패드는복수의필름도선과각각전기적으로연결된다. 복수의필름도선은상부덮개및 하부덮개사이에서한 개의층으로배치된다. 복수의필름도선각각은제 1 장변의아래를가로질러배치된다. 본발명의실시예에따르면, 출력패드의배치의효율이향상될수 있다. 본발명의실시예에따른칩 온필름패키지가디스플레이패널에연결되면, 높은화질특성을갖는디스플레이장치가얻어질수 있다.

Abstract translation: 根据本发明的薄膜封装芯片包括集成电路芯片，其包括沿着第一长边布置的一个或多个基本输出焊盘和沿着第二长边侧布置的一个或多个扩展输出焊盘， 长边。 此外，根据本发明的薄膜封装芯片包括一个薄膜，它包括一个底盖，多个薄膜布线，布置在底盖的一侧，薄膜布线之间有间隔，盖板覆盖 薄膜电线在底盖的一侧。 一个或多个基本输出焊盘和一个或多个扩展输出焊盘电连接到薄膜导线。 薄膜线布置在顶盖和底盖之间作为一层。 每条胶片线布置在第一长边的下侧。 根据本发明的实施例，提高了输出焊盘的布置效率。 如果将根据本发明的实施例的胶片封装的芯片连接到显示面板，则获得具有高图像质量的显示装置。

公开(公告)号：KR1020120063202A

公开(公告)日：2012-06-15

申请号：KR1020100124279

申请日：2010-12-07

Applicant: 삼성전자주식회사

Inventor： 신나래 ,  임소영 ,  김철우 ,  정예정

IPC: H01L23/48 ,  H01L23/50

CPC classification number: H01L23/3107 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/49572 ,  H01L23/49861 ,  H01L2224/73204

Abstract: PURPOSE: A semiconductor package and a display panel assembly including the same are provided to protect a circuit from external impacts, moisture, and chemical materials by forming a protection layer which covers a wiring circuit in an opposite direction to a semiconductor chip around a film. CONSTITUTION: A semiconductor chip(100) is received in a hole between films(300). A passivation layer(750) protects a semiconductor chip from the outside. A metal pad(800) electrically connects the semiconductor chip to the substrate. A molding member(200) covers the semiconductor chip, the metal pad, and the passivation layer. A protection layer(700) is opposite to the semiconductor chip around the film.

Abstract translation: 目的：提供半导体封装和包括该半导体封装的显示面板组件，以通过形成保护层来保护电路免受外部冲击，湿气和化学材料的影响，该保护层覆盖与膜周围的半导体芯片相反的方向。 构成：半导体芯片（100）被容纳在膜（300）之间的孔中。 钝化层（750）从外部保护半导体芯片。 金属焊盘（800）将半导体芯片电连接到基板。 模制构件（200）覆盖半导体芯片，金属焊盘和钝化层。 保护层（700）与膜周围的半导体芯片相对。

公开(公告)号：KR1020080061603A

公开(公告)日：2008-07-03

申请号：KR1020060136524

申请日：2006-12-28

Applicant: 삼성전자주식회사

Inventor： 신나래

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L24/50 ,  H01L23/49811 ,  H01L24/97

Abstract: Film packages comprising at least two stress-adjusting leads on one selected stress-adjusting bump are provided to minimize influence of stress generated in the film packages by using stress control leads corresponded with a stress control bump and a bump thereof. A semiconductor device(70) is disposed on a base film, and connected with the base film electrically through a selected plane. A stress control bump(53,59) is disposed between the semiconductor device and the base film, and limited on the selected plane of the semiconductor device. At least two stress control leads(31,33,37,39) are disposed on the base film so as to be positioned between the stress control bump and the base film.

Abstract translation: 提供了包括在一个选定的应力调节凸块上的至少两个应力调节引线的薄膜封装，以通过使用与应力控制凸块及其凸块相对应的应力控制引线来最小化在薄膜封装中产生的应力的影响。 半导体器件（70）设置在基膜上，并通过选定的平面与基膜电连接。 应力控制凸起（53,59）设置在半导体器件和基底膜之间，并限制在半导体器件的选定平面上。 至少两个应力控制引线（31,33,37,39）设置在基膜上，以便位于应力控制凸块和基膜之间。

公开(公告)号：KR102252380B1

公开(公告)日：2021-05-14

申请号：KR1020140049462

申请日：2014-04-24

Applicant: 삼성전자주식회사

Inventor： 정재민 ,  신나래

IPC: H01L21/60 ,  H01L23/48

Abstract: 본발명의기술적사상은테이프배선기판을이용하는반도체패키지에있어서, 더미칩 영역을포함하여폭이증가한반도체칩을적용하면서도테이프배선기판의사이즈증가를최소화할수 있는배선패턴을갖는테이프배선기판, 반도체패키지및 상기반도체패키지를포함한디스플레이장치를제공한다. 그반도체패키지는, 중앙부분에배치되고칩 배선들에연결된패드들이형성된유효칩 영역과, 상기유효칩 영역의측면에배치되고상기칩 배선들에연결되지않은패드들이형성된더미칩 영역을구비한반도체칩; 상기반도체칩이실장되는칩 실장부를구비하는베이스필름; 및상기베이스필름상에형성되고상기반도체칩의상기칩 배선들에전기적으로연결된다수의배선패턴들;을포함하고, 상기다수의배선패턴들중 일부인제1 배선패턴들은상기더미칩 영역하부의상기칩 실장부의제1 부분을통과한다.

公开(公告)号：KR1020140131741A

公开(公告)日：2014-11-14

申请号：KR1020130050718

申请日：2013-05-06

Applicant: 삼성전자주식회사

Inventor： 양경숙 ,  하정규 ,  이파란 ,  신나래 ,  임소영 ,  정재민 ,  조경순

IPC: H01L51/50 ,  H05B33/06 ,  G09F9/00

CPC classification number: H05K1/118 ,  H05K1/147 ,  H05K1/189 ,  H05K2201/0949 ,  H05K2201/10128 ,  H01L51/5253 ,  G09F9/00 ,  H01L27/3237 ,  H01L51/5256 ,  H01L51/56 ,  H05B33/06

Abstract: 표시 장치를 제공한다. 표시 장치는, 표시 패널, 후면은 표시 패널과 연결되며, 전면에 칩이 실장된 연성 회로 필름 및 칩과 표시 패널을 전기적으로 연결하는 제1 리드 본딩을 포함하되, 제1 리드 본딩은, 연성 회로 필름 전면에서 칩 및 연성 회로 필름 사이에 배치되는 제1 부분, 연성 회로 필름을 관통하는 제2 부분 및 연성 회로 필름의 후면에서 연성 회로 필름 및 표시 패널 사이에 배치되는 제3 부분을 포함하되, 제3 부분은 상기 제1 부분과 오버랩된다.

Abstract translation: 提供一种显示装置。 显示装置包括显示面板，柔性电路薄膜，其通过其背面连接到显示面板，并且在其前面安装芯片;以及第一引线接合，其将芯片电连接到显示面板。 第一引线接合包括布置在柔性电路膜前面的芯片和柔性电路膜之间的第一部分，穿过柔性电路膜的第二部分和布置在柔性电路膜之间的第三部分 胶片和柔性电路膜背面的显示面板。 第三部分与第一部分重叠。

公开(公告)号：KR1020140108845A

公开(公告)日：2014-09-15

申请号：KR1020130022604

申请日：2013-03-04

Applicant: 삼성전자주식회사

Inventor： 하정규 ,  이관재 ,  정재민 ,  조경순 ,  신나래 ,  양경숙 ,  이파란 ,  임소영

IPC: H01L51/52 ,  H05B33/06 ,  G06F3/041

CPC classification number: G06F3/0412 ,  G06F1/1626 ,  G06F1/1637 ,  G06F1/1643 ,  G06F1/1652 ,  G06F3/0416 ,  G06F2203/04102 ,  H01L27/323 ,  H01L27/3276 ,  H01L2251/5338 ,  H01L27/3255

Abstract: A chip-on film package comprises a ductile base film having a first surface and a second surface which face each other and forming at least one penetration hole. A plurality of wires are respectively formed on the first surface and the second surface of the base film and have a first lead and a second lead which are connected to each other through the penetration hole. Each operating chip for a display panel and sensor chip for a touch panel is mounted on either the first surface or the second surface of the base film, and either the driving chip for the display panel or the sensor chip for the touch panel is electrically connected with the first and second lead.

Abstract translation: 贴片胶片包装包括具有第一表面和第二表面的延性基膜，所述第一表面和第二表面彼此面对并形成至少一个穿透孔。 多个电线分别形成在基膜的第一表面和第二表面上，并且具有通过贯通孔彼此连接的第一引线和第二引线。 用于显示面板的每个操作芯片和用于触摸面板的传感器芯片安装在基膜的第一表面或第二表面上，用于显示面板的驱动芯片或用于触摸面板的传感器芯片电连接 第一和第二个领先。

公开(公告)号：KR1020140025851A

公开(公告)日：2014-03-05

申请号：KR1020120092056

申请日：2012-08-23

Applicant: 삼성전자주식회사

Inventor： 하정규 ,  이관재 ,  정재민 ,  조경순 ,  신나래 ,  양경숙 ,  이파란 ,  임소영

IPC: H01L23/12 ,  H01L21/60 ,  G02F1/1345

CPC classification number: H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A COF substrate includes a base film, first upper conductive patterns, at least one second upper conductive pattern, and lower conductive patterns. The first upper conductive patterns are arranged in the upper surface of the base film. Each first upper conductive pattern includes a separated inner pattern and an outer pattern. The second conductive pattern is arranged to be located between the first upper conductive patterns in the upper surface of the base film. The lower conductive patterns are arranged in the lower surface of the base film and connect the inner pattern and the outer pattern. Therefore, the generation of the short between panel patterns having micro pitches is prevented by a COF substrate structure.

Abstract translation: COF基板包括基膜，第一上导电图案，至少一个第二上导电图案和下导电图案。 第一上导电图案布置在基膜的上表面中。 每个第一上导电图案包括分离的内图案和外图案。 第二导电图案被布置成位于基膜的上表面中的第一上导电图案之间。 下导电图案布置在基膜的下表面中并连接内图案和外图案。 因此，通过COF基板结构防止了具有微距的面板图案之间的短路的产生。

公开(公告)号：KR1020080030874A

公开(公告)日：2008-04-07

申请号：KR1020060097407

申请日：2006-10-02

Applicant: 삼성전자주식회사

Inventor： 신나래

IPC: H01L21/60

CPC classification number: H01L24/50 ,  H01L2224/50

Abstract: A tape wiring substrate for a film type semiconductor package is provided to increase the pattern pitch of outer leads or reduce film length by making test pads arranged in row and column directions on a base film to shift positions of inner connection leads. A tape wiring substrate(100) for a film type semiconductor package comprises a plurality of outer leads(OL), a plurality of inner connection leads for a test pad, and a plurality of test pads(TP). The outer leads are formed on a base film. The inner connection leads for a test pad are respectively connected to the outer leads. The test pads are respectively connected to the inner connection leads for testing pattern quality of the outer leads formed on the base film. The test pads are arranged in row and column directions, and symmetrically placed on opposite sides from a reference point positioned in the row direction on the base film.

Abstract translation: 提供了一种用于薄膜型半导体封装的胶带布线基板，通过使基片上的行和列方向上布置的测试焊盘移动到内部连接引线的位置来增加外部引线的图案间距或减小膜长度。 用于薄膜型半导体封装的带状布线基板（100）包括多个外部引线（OL），多个用于测试焊盘的内部连接引线和多个测试焊盘（TP）。 外引线形成在基膜上。 用于测试焊盘的内部连接引线分别连接到外部引线。 测试焊盘分别连接到内部连接引线，以测试形成在基膜上的外部引线的图案质量。 测试垫被排列成行和列方向，并且对称地放置在基底上位于行方向上的参考点的相对侧上。

公开(公告)号：KR100809704B1

公开(公告)日：2008-03-06

申请号：KR1020060092455

申请日：2006-09-22

Applicant: 삼성전자주식회사

Inventor： 신나래 ,  김동한

IPC: H01L21/60 ,  H01L23/48

CPC classification number: H01L23/4985 ,  H01L23/544 ,  H01L24/50 ,  H01L24/86 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014

Abstract: A semiconductor package with improved assembly accuracy is provided to prevent deformation of a tape due to pressurization and heating by respectively forming dummy patterns on a semiconductor chip and a tape substrate on which the semiconductor chip is mounted. A semiconductor chip(210) has a first connecting terminal arranged on one surface. A tape substrate has a base member(110) and a second connecting terminal. The tape substrate is arranged on the base member. The second connecting terminal is arranged by corresponding to the first connecting terminal. A first fixing member(231) is arranged on a surface of the semiconductor chip. A second fixing member(131) is arranged on the base member. The second fixing member is arranged by corresponding to the first fixing member. The tape substrate is a chip-on-film type tube substrate. The first fixing member has a pump-shaped dummy pattern. The second fixing member has a pair of lead-shaped dummy patterns.

Abstract translation: 提供了具有改进的组装精度的半导体封装，以防止在半导体芯片上分别形成虚设图案的加压和加热导致的带变形，以及安装半导体芯片的带基板。 半导体芯片（210）具有布置在一个表面上的第一连接端子。 带基材具有基底构件（110）和第二连接端子。 带基材布置在基底构件上。 第二连接端子对应于第一连接端子布置。 第一固定构件（231）布置在半导体芯片的表面上。 第二固定构件（131）布置在基座构件上。 第二固定构件相对于第一固定构件布置。 带基材是片上胶片型管基片。 第一固定构件具有泵状虚拟图案。 第二固定构件具有一对引线形虚拟图案。

公开(公告)号：KR100761853B1

公开(公告)日：2007-09-28

申请号：KR1020060067101

申请日：2006-07-18

Applicant: 삼성전자주식회사

Inventor： 이희석 ,  최윤석 ,  송은석 ,  조영상 ,  신나래

IPC: G02F1/1345

CPC classification number: H01F21/12 ,  H01F41/045 ,  H05K1/147 ,  H05K1/165

Abstract: A repairable and scalable filter, a tape line substrate with the filter and a display panel assembly with the tape line substrate are provided to effectively reduce the EMI(Electromagnetic Interference) and to maintain the driving property of a driving driver IC(Integrated Circuit) by mounting the repairable and scalable filter within wiring lines and repairing the filter to have a predetermined inductance corresponding to the generation of the EMI. A base film(161) has a chip mounting member for mounting a semiconductor chip. A wiring pattern(180) is arrayed on the base film. A filter is arrayed on the base film adjacent to the wiring pattern. The filter includes a filter wiring line(210) with the first line width and having the first and second ends. Repair members(220) are arrayed between the first and second ends of the filter wiring line. A filter bank member(230) is connected between the first and second ends of the filter wiring lines and controls the inductance of the filter according to the repair of the repairing member. The repair members have one or more repair patterns with the second line width. The filter bank member includes one or more unit bank filters connected in parallel to the repair patterns of the repair members. The unit filter banks have one of meander, spiral or solenoid shapes.

Abstract translation: 提供可修复和可缩放的滤波器，具有滤波器的带线基板和带带线基板的显示面板组件，以有效降低EMI（电磁干扰），并通过以下方式保持驱动驱动器IC（集成电路）的驱动性能 将可修复和可缩放的滤波器安装在布线内，并修复滤波器以具有对应于EMI产生的预定电感。 基膜（161）具有用于安装半导体芯片的芯片安装部件。 布线图案（180）排列在基膜上。 滤光片排列在邻近布线图案的基片上。 滤波器包括具有第一线宽并具有第一端和第二端的滤波器布线（210）。 维修构件（220）排列在过滤器配线的第一和第二端之间。 滤波器组构件（230）连接在滤波器布线的第一端和第二端之间，并且根据修理构件的修理来控制滤波器的电感。 修理构件具有一个或多个具有第二线宽度的修复图案。 过滤器组件包括与修理构件的修复图案并联连接的一个或多个单元组过滤器。 单元滤波器组具有曲折，螺旋形或螺线形形状之一。