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公开(公告)号：KR1020030065702A
公开(公告)日：2003-08-09
申请号：KR1020020005423
申请日：2002-01-30
Applicant: 삼성전자주식회사
IPC: H01L29/788
Abstract: PURPOSE: A method for fabricating a floating gate type non-volatile memory device is provided to increase the capacitance between a floating gate electrode and a control gate electrode and enhance a coupling ratio by forming an insulating layer having a high dielectric constant between the floating gate electrode and the control gate electrode. CONSTITUTION: An isolation layer(6) is formed on a predetermined region of a semiconductor substrate(1) in order to define an active region. A tunnel oxide layer(2) and a floating gate line are sequentially stacked on an upper portion of the active region. A dielectric layer(9) including an insulating layer is formed on the entire surface of the semiconductor substrate including the floating gate line. A dielectric constant of the insulating layer is higher than the dielectric constant of a silicon nitride layer. A conductive layer of control gate is formed on the dielectric layer. A floating gate electrode(8a), the dielectric layer, and a control gate electrode(12) are formed by patterning sequentially the conductive layer of control gate, the dielectric layer, and the floating gate line.
Abstract translation: 目的：提供一种用于制造浮动栅型非易失性存储器件的方法，以增加浮栅和控制栅电极之间的电容，并通过在浮置栅极之间形成具有高介电常数的绝缘层来提高耦合比 电极和控制栅电极。 构成：为了限定有源区，在半导体衬底（1）的预定区域上形成隔离层（6）。 隧道氧化物层（2）和浮栅线依次层叠在有源区的上部。 在包括浮动栅极线的半导体衬底的整个表面上形成包括绝缘层的电介质层（9）。 绝缘层的介电常数高于氮化硅层的介电常数。 在电介质层上形成控制栅的导电层。 通过对控制栅极，电介质层和浮置栅极线的导电层顺序构图，形成浮栅电极（8a），电介质层和控制栅电极（12）。
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公开(公告)号：KR1020020080582A
公开(公告)日：2002-10-26
申请号：KR1020010020219
申请日：2001-04-16
Applicant: 삼성전자주식회사
IPC: H01L21/70
Abstract: PURPOSE: A method for fabricating a non-volatile memory(NVM) device is provided to improve cell distribution by reducing increase of the thickness of an interlayer dielectric. CONSTITUTION: A tunnel oxide layer(102) is formed on a semiconductor substrate(100). The first conductive layer for a floating gate is formed on the tunnel oxide layer. An interlayer dielectric(112) is formed on the first conductive layer. The second conductive layer for a control gate is formed on the interlayer dielectric. A hard mask layer pattern for defining a gate region is formed on the second conductive layer. The second conductive layer and the interlayer dielectric are etched to form the control gate by using the hard mask layer pattern as an etch mask. A part of the first conductive layer is etched by using the hard mask layer pattern as an etch mask. Impurity ions(120) are implanted into the resultant structure so that the exposed surface of the first conductive layer and the exposed side surface of the control gate are doped. The remaining first conductive layer is etched to form the floating gate by using the hard mask layer pattern as an etch mask. The side surfaces of the floating gate and the control gate are oxidized.
Abstract translation: 目的：提供一种用于制造非易失性存储器（NVM）器件的方法，以通过减少层间电介质厚度的增加来改善电池分布。 构成：在半导体衬底（100）上形成隧道氧化物层（102）。 用于浮置栅极的第一导电层形成在隧道氧化物层上。 在第一导电层上形成层间电介质（112）。 用于控制栅极的第二导电层形成在层间电介质上。 用于限定栅极区域的硬掩模层图案形成在第二导电层上。 通过使用硬掩模层图案作为蚀刻掩模，蚀刻第二导电层和层间电介质以形成控制栅极。 通过使用硬掩模层图案作为蚀刻掩模蚀刻第一导电层的一部分。 将杂质离子（120）注入到所得结构中，使得第一导电层的暴露表面和控制栅极的暴露侧表面被掺杂。 通过使用硬掩模层图案作为蚀刻掩模，蚀刻剩余的第一导电层以形成浮置栅极。 浮动栅极和控制栅极的侧面被氧化。
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公开(公告)号：KR1020020010830A
公开(公告)日：2002-02-06
申请号：KR1020000044325
申请日：2000-07-31
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: PURPOSE: A method for manufacturing a capacitor of a semiconductor memory device is provided to prevent a cylindrical lower electrode from being damaged by a defect, by controlling a hemispherical grain(HSG) growth on the outer wall of the cylindrical lower electrode while minimizing damage to the cylindrical lower electrode. CONSTITUTION: A mold layer pattern exposing a predetermined region on a semiconductor substrate(100) is formed on the semiconductor substrate. The cylindrical lower electrode is formed in the predetermined region. An HSG growth control layer composed of polysilicon forms the outer wall of the lower electrode. A doped polysilicon layer forms the inner layer of the lower electrode. An HSG layer(136) constitutes the inner wall of the lower electrode, formed on the doped polysilicon layer. The mold layer pattern is eliminated. A dielectric layer(150) is formed on the lower electrode. An upper electrode(160) is formed on the dielectric layer.
Abstract translation: 目的：提供一种用于制造半导体存储器件的电容器的方法，以通过控制圆柱形下电极的外壁上的半球形晶粒（HSG）生长来防止圆柱形下电极被缺陷损坏，同时最小化对 圆柱形下电极。 构成：在半导体衬底上形成露出半导体衬底（100）上的预定区域的模层图案。 圆筒形下电极形成在预定区域中。 由多晶硅构成的HSG生长控制层形成下电极的外壁。 掺杂多晶硅层形成下电极的内层。 HSG层（136）构成形成在掺杂多晶硅层上的下电极的内壁。 消除模层图案。 在下电极上形成介电层（150）。 在电介质层上形成上电极（160）。
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公开(公告)号：KR1020010083697A
公开(公告)日：2001-09-01
申请号：KR1020000008185
申请日：2000-02-21
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A method for manufacturing a capacitor electrode of a semiconductor device is provided to improve a leakage current characteristic of a capacitor, by making a dielectric layer and the first upper electrode react with each other in a deposition process of the first upper electrode or subsequent heat treatment process so that the dielectric layer is not deteriorated. CONSTITUTION: A lower electrode(118) is formed on a semiconductor substrate(100). A dielectric layer(122) is formed on the lower electrode. The first upper electrode(124) is formed on the dielectric layer at a temperature not higher than 600 deg.C. An annealing process is performed regarding the resultant structure having the first upper electrode in an atmosphere of ozone, oxygen or oxygen plasma and at a temperature not higher than a predetermined temperature wherein the first upper electrode is not oxidized. The second upper electrode(126) is formed on the first upper electrode.
Abstract translation: 目的：提供一种用于制造半导体器件的电容器电极的方法，以通过在第一上电极或随后的第一上电极的沉积工艺中使电介质层和第一上电极彼此反应来改善电容器的漏电流特性 热处理工艺，使得介电层不劣化。 构成：在半导体衬底（100）上形成下电极（118）。 电介质层（122）形成在下电极上。 第一上电极（124）在不高于600℃的温度下形成在电介质层上。 在臭氧，氧气或氧气等离子体的气氛中，在不高于第一上部电极未被氧化的预定温度的温度下，对具有第一上部电极的结果进行退火处理。 第二上电极（126）形成在第一上电极上。
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公开(公告)号：KR1020010048683A
公开(公告)日：2001-06-15
申请号：KR1019990053469
申请日：1999-11-29
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: PURPOSE: A method for manufacturing a capacitor storage electrode of a semiconductor device is provided to form the storage electrode suitable for a high integrated semiconductor capacitor, by maximizing an effective area of the capacitor storage electrode, and by simplifying a process for forming the storage electrode. CONSTITUTION: A conductive material is filled in a contact in which a predetermined region of a substrate(100) is exposed between word lines, to form a pad(112). The first etch stop layer is formed in a portion except the pad. After the second insulating layer(114) is deposited on the first etch stop layer and the pad, a bit line(116) is formed. After the bit line is formed, the second etch stop layer is formed. The third insulating layer filling a curved portion between bit lines is formed on the second etch stop layer. The fourth insulating layer(124) is deposited on the third insulating layer, and etched to form a storage electrode region by a photolithography process. A conductive material is deposited on the entire substrate including the fourth insulating layer to form a storage electrode layer. The storage electrode layer deposited on the surface of the fourth insulating layer is removed, and the fourth insulating layer is exposed to separate the storage electrode.
Abstract translation: 目的：提供一种用于制造半导体器件的电容器存储电极的方法，以通过最大化电容器存储电极的有效面积，并且简化用于形成存储电极的工艺来形成适用于高集成半导体电容器的存储电极 。 构成：导电材料填充在基板（100）的预定区域在字线之间露出的接触中，以形成焊盘（112）。 第一蚀刻停止层形成在除了焊盘之外的部分中。 在第二绝缘层（114）沉积在第一蚀刻停止层和焊盘上之后，形成位线（116）。 在形成位线之后，形成第二蚀刻停止层。 填充位线之间的弯曲部分的第三绝缘层形成在第二蚀刻停止层上。 第四绝缘层（124）沉积在第三绝缘层上，并通过光刻工艺进行蚀刻以形成存储电极区域。 在包括第四绝缘层的整个基板上沉积导电材料以形成存储电极层。 去除沉积在第四绝缘层的表面上的存储电极层，暴露第四绝缘层以分离存储电极。
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Patent Agency Ranking
公开(公告)号：KR100269332B1
公开(公告)日：2000-10-16
申请号：KR1019980027317
申请日：1998-07-07
Applicant: 삼성전자주식회사
IPC: H01L27/04
Abstract: 상부전극과 하부전극사이에 다층 유전막이 형성되어 있되, 그 중간층에 비정질층이 형성되어 있는 반도체 장치의 커패시터 및 그 제조방법이 개시되어 있다. 다층 유전막의 중간에 상기 비정질층이 형성되어 있어, 상기 비정질층 상에 형성된 유전막에 보이드와 같은 결함이 형성되더라도, 이러한 결함이 상기 비정질층 아래에 형성된 유전막 및 하부전극에 까지 퍼지는 것을 방지할 수 있다. 따라서, 커패시터의 유전막 누설전류 특성이 개선될 수 있고, 반도체 장치가 오동작되는 것이 방지될 수 있다.
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公开(公告)号：KR1019990085684A
公开(公告)日：1999-12-15
申请号：KR1019980018239
申请日：1998-05-20
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: 커패시터의 하부전극을 형성하는 과정에서 매몰 콘택 상부의 결정화를 억제하고, 공정 처리 시간(throughput time)을 단축할 수 있는 커패시터 하부 전극 형성방법에 관해 개시한다. 이를 위해 본 발명은 절연막에 콘택홀이 형성된 반도체 기판에 불순물이 포함되지 않은 제1 실리콘층을 형성하고, 제1 실리콘층 위에 불순물이 포함된 제2 실리콘층을 형성한 후, 제1 및 제2 실리콘층을 패터닝하여 커패시터 하부전극을 형성하는 공정을 구비하는 커패시터 하부전극 형성방법을 제공한다. 여기서, 제1 실리콘층으로 불순물이 포함된 실리콘층을 사용하고, 제2 실리콘층으로 불순물이 포함되지 않은 실리콘층을 사용할 수 있다.
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公开(公告)号：KR100123734B1
公开(公告)日：1997-11-25
申请号：KR1019940012153
申请日：1994-05-31
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: A method of forming an isolation region according to high-temperature heat treatment in nitrogen ambient includes the steps of forming an oxide layer on a semiconductor substrate, forming a buffer silicon layer on the oxide layer, forming an oxidation stopping layer on the buffer silicon layer, patterning the oxidation stopping layer and buffer silicon layer into an active region pattern to form a contact hole exposing the buffer silicon layer, performing thermal oxidation to form a capping oxide layer for preventing defects from generating due to nitrogen pitting on the exposed buffer silicon layer, carrying out high-temperature heat treatment at above 1100 deg C in nitrogen ambient to form an oxynitride layer between the capping oxide layer and buffer silicon layer, and performing thermal oxidation to form an isolation region.
Abstract translation: 在氮气环境中根据高温热处理形成隔离区域的方法包括以下步骤：在半导体衬底上形成氧化物层，在氧化物层上形成缓冲硅层，在缓冲硅层上形成氧化停止层 图案化氧化停止层并将硅层缓冲成有源区域图案以形成暴露缓冲硅层的接触孔，进行热氧化以形成覆盖氧化物层，以防止由于暴露的缓冲硅层上的氮点蚀而产生的缺陷 在氮环境中在1100℃以上进行高温热处理，在封盖氧化层和缓冲硅层之间形成氧氮化物层，进行热氧化，形成隔离区。
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公开(公告)号：KR1020110122523A
公开(公告)日：2011-11-10
申请号：KR1020100042081
申请日：2010-05-04
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L27/11578 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L27/10852 , H01L27/11582 , H01L28/91 , H01L29/66833 , H01L29/7926 , H01L21/823487
Abstract: PURPOSE: A semiconductor memory device and a manufacturing method thereof are provided to secure the uniformity of a cell current by forming semiconductor patterns with excellent step coating. CONSTITUTION: A buffer insulating film(105) is formed on a semiconductor substrate(100). A thin film structure is formed on the buffer insulating film and consists of a plurality of thin films. The thin film structure is patterned and a penetration area(130) is formed on the thin film structure. A first silicon film(152) is formed to cover the penetration area. A second silicon film(154) is formed on the first silicon film.
Abstract translation: 目的：提供半导体存储器件及其制造方法，以通过形成具有优异的阶梯涂布的半导体图案来确保电池电流的均匀性。 构成：在半导体衬底（100）上形成缓冲绝缘膜（105）。 在缓冲绝缘膜上形成薄膜结构，由多个薄膜构成。 图案化薄膜结构，并且在薄膜结构上形成穿透区域（130）。 形成第一硅膜（152）以覆盖穿透区域。 在第一硅膜上形成第二硅膜（154）。
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公开(公告)号：KR100897288B1
公开(公告)日：2009-05-14
申请号：KR1020060102580
申请日：2006-10-20
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L29/7881 , H01L21/28273 , H01L29/42324 , H01L29/513 , H01L29/66825
Abstract: 비휘발성 메모리 소자 및 그 형성방법이 제공된다. 상기 비휘발성 메모리 소자의 형성방법은 반도체 기판 상에 터널링 절연막을 형성하는 것 그리고 플루오르를 포함하는 플라즈마 공정을 진행하는 것을 포함한다.
플라즈마 공정, 터널링 절연 패턴, 층간 절연 패턴, 신뢰성
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