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公开(公告)号：KR1020140048026A
公开(公告)日：2014-04-23
申请号：KR1020130029769
申请日：2013-03-20
Applicant: 한국전자통신연구원
IPC: H01L21/3205 , H01L21/28 , H01L21/768
CPC classification number: H01L21/76898 , H01L21/76877 , H01L23/481 , H01L23/535
Abstract: A semiconductor device according to the concept of the present invention may include a substrate having a lower via hole; an epi layer which has an opening part for exposing the upper surface of the substrate; a semiconductor chip which is provided on the upper surface of the substrate and includes a first electrode, a second electrode, and a third electrode; an upper metal layer connected to the first electrode; a support plate which is arranged on the upper metal layer and has an upper via hole; an upper pad which is arranged on the support substrate and is extended to the inner part of the upper via hole; a lower pad which is arranged in the opening pad and is connected to the second electrode; and a lower metal layer which covers the lower surface of the substrate and is connected to the lower pad through the lower via hole.
Abstract translation: 根据本发明的概念的半导体器件可以包括具有下通孔的衬底; 外延层，其具有用于使基板的上表面露出的开口部; 半导体芯片，其设置在所述基板的上表面，并且包括第一电极，第二电极和第三电极; 连接到第一电极的上金属层; 支撑板，其设置在上金属层上并具有上通孔; 上垫，其布置在所述支撑基板上并延伸到所述上通孔的内部; 下垫，其布置在所述开口垫中并连接到所述第二电极; 以及覆盖基板的下表面并通过下通孔连接到下焊盘的下金属层。
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公开(公告)号：KR1020130093996A
公开(公告)日：2013-08-23
申请号：KR1020120015292
申请日：2012-02-15
Applicant: 한국전자통신연구원
CPC classification number: H01L21/8222 , H01G7/00 , H01L27/0647 , H01L27/0658 , H01L29/93 , H03F1/565 , H03F3/21 , H03F2200/36 , H03F2200/378 , H03F2200/387 , H03F2200/391 , H03H7/38 , Y10T29/43
Abstract: PURPOSE: An impedance matching circuit including passive elements for controlling the matching property, an amplification circuit and a manufacturing method of a variable capacitor are provided to modify the characteristic value of passive elements included in the multi-staged impedance matching circuit, so that a broadband matching realizes. CONSTITUTION: A first variable inductor part (L1) is connected between the output terminal of a first node (N1) and an amplifying unit (AMP). A second variable inductor part (L2) is connected between the first node and a second Node (N2). The inductance value of the first variable inductor part and the second variable inductor part is determined according to the number and the length of wires. A first variable capacitor portion (C1) is connected between the first node and a ground voltage platform. A second variable capacitor portion (C2) is connected between the second node and the ground voltage platform. [Reference numerals] (AMP) Power amplifying unit
Abstract translation: 目的：提供一种阻抗匹配电路，其包括用于控制匹配特性的无源元件，放大电路和可变电容器的制造方法，以修改包括在多级阻抗匹配电路中的无源元件的特性值，使得宽带 匹配实现。 构成：第一可变电感器部分（L1）连接在第一节点（N1）的输出端和放大单元（AMP）之间。 第二可变电感器部分（L2）连接在第一节点和第二节点（N2）之间。 根据导线的数量和长度确定第一可变电感器部分和第二可变电感器部分的电感值。 第一可变电容器部分（C1）连接在第一节点和地电压平台之间。 第二可变电容器部分（C2）连接在第二节点和地电压平台之间。 （附图标记）（AMP）功率放大单元
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公开(公告)号：KR1020130066934A
公开(公告)日：2013-06-21
申请号：KR1020110133715
申请日：2011-12-13
Applicant: 한국전자통신연구원
IPC: H01L21/338 , H01L29/812
CPC classification number: H01L29/0649 , H01L21/28593 , H01L29/402 , H01L29/42316 , H01L29/66462 , H01L29/7786
Abstract: PURPOSE: A semiconductor device including a step gate electrode and a manufacturing method thereof are provided to increase a breakdown voltage by using optical photoresist and two nitride layers. CONSTITUTION: A cap layer(211) is formed on a semiconductor substrate. An active area is formed by etching a part of the cap layer. A resist pattern is formed on the active area and the cap layer. A step gate electrode(225) is formed by depositing heat-resistant metal. An insulation layer(227) is deposited by removing a gate head pattern.
Abstract translation: 目的：提供包括步进栅电极及其制造方法的半导体器件，以通过使用光致抗蚀剂和两个氮化物层来增加击穿电压。 构成：在半导体衬底上形成覆盖层（211）。 通过蚀刻盖层的一部分形成有源区。 在有源区域和盖层上形成抗蚀剂图案。 通过沉积耐热金属形成步进栅电极（225）。 通过去除栅极头图案来沉积绝缘层（227）。
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公开(公告)号：KR1020120068599A
公开(公告)日：2012-06-27
申请号：KR1020100130291
申请日：2010-12-17
Applicant: 한국전자통신연구원
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/7831 , H01L29/2003 , H01L29/404 , H01L29/42316 , H01L29/66462 , H01L29/66863 , H01L29/7787 , H01L29/812 , H01L29/7783
Abstract: PURPOSE: A field effect transistor and a manufacturing method thereof are provided to control an insulation film property of the lower side of an electric field electrode by controlling the thickness of an insulation film on the lower side of each electric field electrode in a field effect transistor. CONSTITUTION: A source electrode, a drain electrode, and a gate electrode are formed on the upper side of a semiconductor substrate(20). A multilayer electric field electrode pattern with a different exposure layer with an opening unit is formed by depositing and patterning a multilayer photosensitive film on the upper side of an insulation film(27). An insulation film with a different step is formed by an insulation film etching process using an electric field electrode pattern as an etch mask. An electric field electrode(30a,30b,30c) is formed on the upper side of the insulation film by lifting off a metal layer after the metal layer is deposited by using the electric field pattern.
Abstract translation: 目的：提供场效应晶体管及其制造方法，以通过控制场效应晶体管中每个电场电极下侧的绝缘膜的厚度来控制电场电极的下侧的绝缘膜性质 。 构成：在半导体衬底（20）的上侧形成源电极，漏电极和栅电极。 通过在绝缘膜（27）的上侧上沉积和图案化多层感光膜，形成具有开口单元的不同曝光层的多层电场电极图案。 通过使用电场电极图案作为蚀刻掩模的绝缘膜蚀刻工艺形成具有不同台阶的绝缘膜。 通过使用电场图案沉积金属层之后，通过剥离金属层，在绝缘膜的上侧形成电场电极（30a，30b，30c）。
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公开(公告)号：KR1020120062346A
公开(公告)日：2012-06-14
申请号：KR1020100123566
申请日：2010-12-06
Applicant: 한국전자통신연구원
IPC: H01L21/8252 , H01L29/423 , H01L29/66 , H01L29/778 , H01L27/06
CPC classification number: H01L29/7783 , H01L21/8252 , H01L27/0605 , H01L29/42316 , H01L29/66462
Abstract: PURPOSE: A manufacturing method of a high frequency device structure is provided to reduce initial reaction energy with a substrate material while diffusing Pt/Pd in a thermal process, thereby stably manufacturing a normally-off type high frequency device. CONSTITUTION: A Schottky barrier layer, an etch-stop layer(106), an ohmic layer(107), and an ohmic electrode are formed on a substrate. A first recess is formed in order to expose a part of the etch-stop layer. A second recess is formed in order to expose a part of the Schottky barrier slayer after forming a gate pattern on the first recess. A gate electrode(115) is formed by depositing a heat resistant metal film after forming a super lattice film by alternately depositing Pt and Pd on the second recess and the gate pattern.
Abstract translation: 目的：提供一种高频器件结构的制造方法，以便在热处理中扩散Pt / Pd的同时降低与衬底材料的初始反应能量，从而稳定地制造常闭型高频器件。 构成：在衬底上形成肖特基势垒层，蚀刻停止层（106），欧姆层（107）和欧姆电极。 形成第一凹部以暴露部分蚀刻停止层。 形成第二凹部以便在第一凹部上形成栅极图案之后暴露一部分肖特基势垒屏障。 通过在第二凹部和栅极图案之间交替沉积Pt和Pd，在形成超晶格膜之后沉积耐热金属膜来形成栅电极（115）。
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Patent Agency Ranking
公开(公告)号：KR1020110063151A
公开(公告)日：2011-06-10
申请号：KR1020090120101
申请日：2009-12-04
Applicant: 한국전자통신연구원
CPC classification number: H03F3/245 , H03F1/0261 , H03F1/52 , H03F3/19 , H03F3/211 , H03F2200/18 , H03F2200/451
Abstract: PURPOSE: A power amplifying apparatus is provided to acquire high stability by adding resistors connected to bases of transistors. CONSTITUTION: A cutoff part(10) is connected between a signal input terminal(1b) and an amplification adjusting part(20). The cutoff part includes a plurality of capacitors(C1-Cn). The cutoff part intercepts a DC component supplied from the signal input terminal. The amplification adjusting part is connected between a bias input terminal(1a) and a circuit protecting part(30). The amplification adjusting part includes a plurality of resistors(R31-R3n). The amplification adjusting part transfers a DC bias voltage from the bias terminal to the circuit protecting part. The circuit protecting part is connected to the cutoff part, the amplification adjusting part and an amplifier(40). The amplifier amplifies the signal transferred from the circuit protecting part.
Abstract translation: 目的：提供功率放大装置，通过添加连接到晶体管基极的电阻来获得高稳定性。 构成：在信号输入端子（1b）和放大调整部件（20）之间连接有截止部分（10）。 截止部分包括多个电容器（C1-Cn）。 截止部分截取从信号输入端子提供的直流分量。 放大调整部连接在偏置输入端子（1a）和电路保护部件（30）之间。 放大调整部包括多个电阻（R31〜R3n）。 放大调整部将偏置端子的直流偏置电压传递到电路保护部。 电路保护部分连接到截止部分，放大调节部分和放大器（40）。 放大器放大从电路保护部分传送的信号。
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公开(公告)号：KR1020050057833A
公开(公告)日：2005-06-16
申请号：KR1020030090037
申请日：2003-12-11
Applicant: 한국전자통신연구원
IPC: H03D7/12
Abstract: 믹서 회로를 제공한다. 본 발명의 믹서 회로는 소스 단자를 접지하는 전계 효과 트랜지스터와, 상기 전계 효과 트랜지스터의 소스 단자에 접속되고, LO 신호를 상기 전계 효과 트랜지스터에 전달하는 LO 정합 회로와, 상기 전계 효과 트랜지스터의 소스 단자에 접속되고, LO 신호를 입력 받아 LO 정합 회로를 통하여 LO 주파수 대역의 신호를 상기 전계 효과 트랜지스터에 공급하는 신호 결합기 회로를 포함한다. 그리고, 본 발명의 믹서 회로는 상기 전계 효과 트랜지스터의 게이트 단자에 연결되고, IF 신호를 입력 받아 IF신호를 상기 전계 효과 트랜지스터에 전달하는 IF 정합 회로와, 상기 전계 효과 트랜지스터의 게이트 단자에 연결되어 바이어스를 가할 수 있는 게이트 바이어스 회로와, 상기 전계 효과 트랜지스터의 드레인 단자에 연결되어 바이어스를 가할 수 있는 드레인 바이어스 회로와, 상기 전계 효과 트랜지스터의 드레인 단자에 연결되어, RF 신호를 RF 출력 단자로 전달하는 RF 정합 회로를 구비한다. 본 발명의 믹서 회로는 LO 신호의 삽입 손실을 감소시키고 DC 차단과 동시에 저주파수 대역의 불요신호의 영향을 차단할 수 있고, LO 신호의 누설에 기인한 신호 변형 특성을 개선할 수 있다.
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公开(公告)号：KR1020040054435A
公开(公告)日：2004-06-25
申请号：KR1020020081473
申请日：2002-12-18
Applicant: 한국전자통신연구원
IPC: H03F3/189
CPC classification number: H03F3/605
Abstract: PURPOSE: An ultrahigh frequency power amplifier is provided to improve a characteristic of undesired gain and a characteristic of input reflection loss in a low frequency band by using a sub-feedback circuit, an RC parallel circuit, and a shunt resistor. CONSTITUTION: An ultrahigh frequency power amplifier includes a first and a second driving amplifier, a first and a second matching circuit, and a power amplifier. The first and the second driving amplifiers(220,222) include a power element, a gate and a drain bias circuit of the power element, an RC parallel circuit connected between the gate of the power element and an input port, a shunt resistor connected between the gate of the power element and the ground, and a sub-feedback circuit connected in parallel to the power element. The first and the second intermediate matching circuits(208,210) are connected to the first and the second driving amplifiers. The power amplifier(224) includes a power distributor, plural power elements, plural gate and drain bias circuits of the power elements, RC parallel circuits connected between the gates of the power elements and the intermediate matching circuits, and a shut resistor connected the gates of the power elements and the ground.
Abstract translation: 目的：提供超高频功率放大器，通过使用子反馈电路，RC并联电路和分流电阻来提高低频带中不希望增益的特性和输入反射损耗的特性。 构成：超高频功率放大器包括第一和第二驱动放大器，第一和第二匹配电路以及功率放大器。 第一和第二驱动放大器（220,222）包括功率元件的功率元件，栅极和漏极偏置电路，连接在功率元件的栅极和输入端口之间的RC并联电路，连接在功率元件 功率元件和接地的栅极，以及与功率元件并联连接的子反馈电路。 第一和第二中间匹配电路（208,210）连接到第一和第二驱动放大器。 功率放大器（224）包括功率分配器，多个功率元件，功率元件的多个栅极和漏极偏置电路，连接在功率元件的栅极和中间匹配电路之间的RC并联电路，以及连接到栅极 的功率元件和地面。
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公开(公告)号：KR100289328B1
公开(公告)日：2001-12-28
申请号：KR1019980053108
申请日：1998-12-04
IPC: H01L29/80
Abstract: 이단계 게이트 리세스(recess) 공정을 이용하여 이단 T-형상의 게이트 구조를 갖는 화합물반도체 소자를 제조하는 방법이 개시된다. 본 발명에 의한 이단계 게이트 리세스 방법을 이용하여 제작된 T-형 게이트에 의하면, 쇼트키 층과 접촉하는 게이트 전극의 게이트 길이가 실제로 게이트 패턴의 길이와 동일하기 때문에 소자의 차단 주파수의 저하없이 고주파 특성을 향상시킬 수 있다. 또한, 본 발명은 2 단의 T-형상의 게이트 전극패턴 하부에 절연막 스페이서를 구비함으로써, 게이트 전극과 소오스/드레인 전극 간의 절연 특성을 향상시킬 수 있다. 그 결과, 신뢰성이 높은 초고속 저잡음의 화합물 반도체 소자를 제작할 수 있다.
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公开(公告)号：KR1020010058252A
公开(公告)日：2001-07-05
申请号：KR1019990062468
申请日：1999-12-27
Applicant: 한국전자통신연구원
IPC: H01L29/778
Abstract: PURPOSE: A method for manufacturing a compound semiconductor device is provided to stably manufacture an asymmetric T-shape gate electrode having a great aspect ratio and a fine gate width. CONSTITUTION: A method for manufacturing a compound semiconductor device sequentially stacks a GaAs buffer layer(13), an InGaAs channel layer(14), a spacer layer(15), a Si-delta doping layer(16), an AlGaAs Schottky layer(17), an undoping AlAs etch stop layer(18), an n-GaAs ohmic layer(19), an n+AlGaAs etch stop layer(20) and an n+GaAs ohmic layer(21) on a semi-insulating GaAs substrate(12). The n+GaAs ohmic layer is selectively etched to form the first recess. A nitride film and resistant-heat metal are sequentially formed on the resulting structure. Portions of the resistant-heat metal and the nitride film are selectively dry-etched. Portions of the resistant-heat metal and the nitride film are selectively dry-etched to form a nitride film pattern having a T shape. The remaining resistant-heat metal is removed to form a T shape insulating film pattern. The n+AlGaAs etch stop layer and the n-GaAs ohmic layer are sequentially etched using the T shape insulating film pattern as an etch mask to form the second recess. A smooth insulating film sidewall having an embossed inclination is formed within the second recess. The undoping AlAs etch stop layer is dry-etched using the insulating film sidewall as a mask to complete the foot of the T shape gate pattern. Photoresist is selectively deposited to form the head of the T shape gate pattern in an asymmetric shape, thus completing the T shape gate pattern. A gate metal is deposited on the completed T shape gate pattern to form an asymmetric T shape gate electrode.
Abstract translation: 目的：提供一种制造化合物半导体器件的方法，以稳定地制造具有大的纵横比和精细的栅极宽度的不对称的T形栅电极。 构成：制造化合物半导体器件的方法顺序堆叠GaAs缓冲层（13），InGaAs沟道层（14），间隔层（15），Si-δ掺杂层（16），AlGaAs肖特基层 17），在半绝缘GaAs衬底上的非掺杂AlAs蚀刻停止层（18），n-GaAs欧姆层（19），n + AlGaAs蚀刻停止层（20）和n + GaAs欧姆层（21） （12）。 选择性地蚀刻n + GaAs欧姆层以形成第一凹槽。 在所得结构上依次形成氮化物膜和耐热金属。 选择性地干蚀刻部分耐热金属和氮化物膜。 选择性地干蚀刻耐电加热金属和氮化物膜的部分以形成具有T形状的氮化物膜图案。 剩余的耐热金属被去除以形成T形绝缘膜图案。 使用T形绝缘膜图案作为蚀刻掩模，依次蚀刻n + AlGaAs蚀刻停止层和n-GaAs欧姆层，以形成第二凹槽。 在第二凹部内形成具有压花倾斜的平滑绝缘膜侧壁。 使用绝缘膜侧壁作为掩模对未掺杂的AlAs蚀刻停止层进行干蚀刻，以完成T形栅极图案的底脚。 选择性地沉积光致抗蚀剂以形成不对称形状的T形栅极图案的头部，从而完成T形栅极图案。 栅极金属沉积在完成的T形栅极图案上以形成不对称的T形栅电极。
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