公开(公告)号：WO2003030253A2

公开(公告)日：2003-04-10

申请号：PCT/US2002/030784

申请日：2002-09-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAMSBEY, Mark, T. ,  SUN, Yu ,  CHANG, Chi

IPC: H01L21/8246

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11531

Abstract: Processes for doping and saliciding word lines (20) in a virtual ground array flash memory device without causing shorting between bit lines (26) are disclosed. According to one aspect, word lines (20) are doped prior to patterning the poly layer from which the word lines (20) are formed in the core region. Thereby, the poly layer protects the substrate between the word lines (20) from doping that could cause shorting between bit lines (26). According to another aspect, word lines (20) are exposed while spacer material, dielectric, or like material protects the substrate between word lines (20). The spacer material or dielectric prevents the substrate from becoming salicided in a manner that, like doping, could cause shorting between bit lines (26). Disclosed are virtual ground array flash memory devices with doped and salicided word lines (20), but no shorting between bit lines (26) even in virtual ground arrays where there are no oxide island isolation regions (28) between bit lines (26).

Abstract translation: 公开了在虚拟接地阵列闪存器件中掺杂和打字字线（20）而不导致位线（26）之间短路的过程。 根据一个方面，在对在芯区域中形成字线（20）的多晶层进行图案化之前，对字线（20）进行掺杂。 因此，多层保护字线（20）之间的衬底免受掺杂，这可能导致位线（26）之间的短路。 根据另一方面，字线（20）被露出，而隔离材料，电介质或类似材料在字线（20）之间保护衬底。 间隔物材料或电介质防止衬底以像掺杂那样在位线（26）之间引起短路的方式变得浸水。 公开了具有掺杂和含水字线（20）的虚拟接地阵列闪存器件，但即使在位线（26）之间没有氧化物岛隔离区域（28）的虚拟接地阵列中也不会在位线（26）之间发生短路。

公开(公告)号：WO2005114734A1

公开(公告)日：2005-12-01

申请号：PCT/US2005/004540

申请日：2005-02-11

Applicant: ADVANCED MICRO DEVICES, INC. ,  QIAN, Weidon ,  RAMSBEY, Mark, T. ,  YANG, Jean, Yee-Mei ,  HADDAD, Sameer

Inventor： QIAN, Weidon ,  RAMSBEY, Mark, T. ,  YANG, Jean, Yee-Mei ,  HADDAD, Sameer

IPC: H01L27/115

CPC classification number: H01L27/115 ,  H01L27/11568

Abstract: The present invention pertains to implementing a dual poly process (500) in forming a transistor based memory device (600). The process allows buried bitlines (662) to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials (670, 674) are also formed over the buried bitlines (662) to improve ( e . g ., increase) a breakdown voltage between the bitlines (662) and wordlines (678), thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process (500) also facilitates a reduction in buried bitline width (666) and thus allows bitlines (662) to be formed closer together. As a result, more devices can be "packed" within the same or a smaller area.

Abstract translation: 本发明涉及在形成基于晶体管的存储器件（600）中实施双重聚合工艺（500）。 该过程允许以比传统位线更少的能量和更浅的深度形成掩埋位线（662），以节省资源和空间，并且改善Vt滚降。 氧化物材料（670,674）也形成在掩埋位线（662）上以改善（例如，增加）位线（662）和字线（678）之间的击穿电压，从而允许编程和擦除电荷之间的更大区分， 更可靠的结果数据存储。 过程（500）还有助于减少掩埋位线宽度（666），从而允许位线（662）更靠近地形成。 因此，更多的设备可以在相同或较小的区域内“打包”。

公开(公告)号：WO2003088353A1

公开(公告)日：2003-10-23

申请号：PCT/US2003/004461

申请日：2003-02-14

Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED

Inventor： RAMSBEY, Mark, T. ,  KAMAL, Tazrien ,  YANG, Jean, Y. ,  LINGUNIS, Emmanuil ,  SHIRAIWA, Hidehiko ,  SUN, Yu

IPC: H01L21/8246

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

Abstract: A method of manufacturing an integrated circuit is provided with a semiconductor substrate (506) having a core region (502) and a periphery region (504). A charge-trapping dielectric layer (510) is deposited in the core region (502), and a gate dielectric layer (522) is deposited in the periphery region (504). Bitlines (518) are formed in the semiconductor substrate (506) in the core region (502) and not in the periphery region (504). A wordline-gate layer (524) is formed and implanted with dopant in the core region (502) and not in the periphery region (504). A wordline (528) and gate (530) are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate (506) around the gate (530), and the gate (530) is implanted with a gate doping implantation in the periphery region (504) and not in the core region (502).

Abstract translation: 集成电路的制造方法具有芯部区域（502）和外围区域（504）的半导体基板（506）。 在芯区域（502）中沉积电荷捕获介电层（510），并且在周边区域（504）中沉积栅介质层（522）。 位线（518）形成在芯区域（502）中的半导体衬底（506）中，而不是在周边区域（504）中。 在芯区域（502）中而不是周边区域（504）中形成并注入掺杂剂的字线栅层（524）。 形成字线（528）和门（530）。 在半导体衬底（506）中围绕栅极（530）注入掺杂剂源极/漏极结，栅极（530）在外围区域（504）而不是在核心区域（502）中注入栅极掺杂注入 ）。

公开(公告)号：WO2003083916A1

公开(公告)日：2003-10-09

申请号：PCT/US2003/001851

申请日：2003-01-21

Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED

Inventor： KAMAL, Tazrien ,  NGO, Minh, Van ,  RAMSBEY, Mark, T. ,  SHIELDS, Jeffrey, A. ,  YANG, Jean, Y. ,  LINGUNIS, Emmanuil ,  SHIRAIWA, Hidehiko ,  HUI, Angela, T.

IPC: H01L21/28

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines (525) (526) formed by using the hard mask extensions (524). A charge-trapping dielectric material (504) is deposited over a semiconductor substrate (501) and first and second bitlines (512) are formed therein. A wordline material (515) and a hard mask material (515) are deposited over the wordline material (515). A photoresist material (518) is deposited over the hard mask material (515) and is processed to form a patterned photoresist material (518). The hard mask material (515) is processed using the patterned photoresist material (518) to form a patterned hard mask material (519). The patterned photoresist is then removed. A hard mask extension material (524) is deposited over the wordline material (515) and is processed to form a hard mask extension (524). The wordline material (515) is processed using the patterned hard mask material (519) and the hard mask extension (524) to form a wordline (525), and the patterned hard mask material (519) and the hard mask extension (524) are then removed.

Abstract translation: 提供一种用于通过使用硬掩模延伸部（524）形成的具有紧密间隔的字线（525）（526）的集成电路存储器的制造方法。 电荷俘获电介质材料（504）沉积在半导体衬底（501）上，并且在其中形成第一和第二位线（512）。 字线材料（515）和硬掩模材料（515）沉积在字线材料（515）上。 光致抗蚀剂材料（518）沉积在硬掩模材料（515）上并被处理以形成图案化的光致抗蚀剂材料（518）。 使用图案化的光致抗蚀剂材料（518）处理硬掩模材料（515）以形成图案化的硬掩模材料（519）。 然后去除图案化的光致抗蚀剂。 硬掩模延伸材料（524）沉积在字线材料（515）上并被处理以形成硬掩模延伸部（524）。 使用图案化的硬掩模材料（519）和硬掩模延伸部（524）来加工字线材料（515）以形成字线（525），并且图案化的硬掩模材料（519）和硬掩模延伸部（524） 然后被删除。

公开(公告)号：WO2003003460A2

公开(公告)日：2003-01-09

申请号：PCT/US2001/049056

申请日：2001-12-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAMSBEY, Mark, T. ,  FLIESLER, Michael ,  RANDOLPH, Mark ,  QIAN, Mimi ,  SUN, Yu

IPC: H01L27/02

CPC classification number: H01L29/7833 ,  H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One aspect of the present invention provides a process for forming IC devices (100) with ESD protection transistors (112). According to one aspect of the invention, an ESD protection transistor (112) is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors (112) that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device (100).

Abstract translation: 本发明的一个方面提供一种用于形成具有ESD保护晶体管（112）的IC器件（100）的工艺。 根据本发明的一个方面，ESD保护晶体管（112）具有轻掺杂，然后在形成间隔物之后进行重掺杂。 具有间隔物的重掺杂可以降低薄层电阻，增强晶体管的双极效应，降低晶体管的电容，并降低结击穿电压，而不会导致短沟道效应。 因此，本发明提供了紧凑，高灵敏度和快速切换的ESD保护晶体管（112）。 间隔物可以与其它晶体管的间隔物同时形成，例如器件（100）的外围区域中的其它晶体管。

公开(公告)号：WO2003001601A2

公开(公告)日：2003-01-03

申请号：PCT/US2001/048825

申请日：2001-12-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAMSBEY, Mark, T. ,  DERHACOBIAN, Narbeh ,  WANG, Janet ,  HUI, Angela ,  PHAM, Tuan ,  SUNKAVALLI, Ravi ,  RANDOLPH, Mark

IPC: H01L27/115

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

Abstract: One aspect of the present invention relates to a method of forming spacers (56) in a SONOS type nonvolatile semiconductor memory device, involving providing a substrate (40) having a core region (42) and periphery region (44), the core region (42) containing SONOS type memory cells (48) and the periphery region (44) containing gate transistors (50); implanting a first implant into the core region (42) and a first implant into the perifery region (44) of the substrate (40); forming a spacer material (52) over the substrate (40); masking the core region (42) and forming spacers (56) adjacent the gate transistors (50) in the perifery region (44); and implanting a second implant into the perifery region (44) of the substrate (40).

Abstract translation: 本发明的一个方面涉及一种在SONOS型非易失性半导体存储器件中形成间隔物（56）的方法，包括提供具有芯区（42）和周边区（44）的基底（40），芯区（ 42），包含SONOS型存储单元（48）和包含栅极晶体管（50）的外围区域（44）; 将第一植入物植入所述芯区域（42）中并将第一植入物植入所述基底（40）的所述外围区域（44）中; 在衬底（40）上形成间隔物（52）; 掩蔽所述芯区域（42）并在所述外形区域（44）中形成与所述栅极晶体管（50）相邻的间隔物（56）。 以及将第二植入物植入到所述基底（40）的外围区域（44）中。

公开(公告)号：EP1250714A1

公开(公告)日：2002-10-23

申请号：EP00984473.9

申请日：2000-12-13

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： PHAM, Tuan, Duc ,  RAMSBEY, Mark, T. ,  SUN, Yu ,  CHANG, Chi

IPC: H01L21/762 ,  H01L21/8239

CPC classification number: H01L21/76202 ,  H01L21/76224 ,  H01L27/1052 ,  Y10S438/981

Abstract: An improved flash memory device, which has shallow trench isolation in the periphery region and LOCOS isolation in the core region is provided. A hard mask is used first to create the shallow trench isolation. The LOCOS isolation is then created. Subsequent etching is used to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide layer. A hard mask is used to prevent nitride contamination of the gate oxide layer.

公开(公告)号：EP1745511A1

公开(公告)日：2007-01-24

申请号：EP05713458.7

申请日：2005-02-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： QIAN, Weidon ,  RAMSBEY, Mark, T. ,  YANG, Jean, Yee-Mei ,  HADDAD, Sameer

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/115 ,  H01L27/11568

Abstract: The present invention pertains to implementing a dual poly process (500) in forming a transistor based memory device (600). The process allows buried bitlines (662) to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials (670, 674) are also formed over the buried bitlines (662) to improve (e.g., increase) a breakdown voltage between the bitlines (662) and wordlines (678), thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process (500) also facilitates a reduction in buried bitline width (666) and thus allows bitlines (662) to be formed closer together. As a result, more devices can be 'packed' within the same or a smaller area.

公开(公告)号：EP1338037A1

公开(公告)日：2003-08-27

申请号：EP01999006.8

申请日：2001-11-15

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： RAMSBEY, Mark, T. ,  YANG, Jean, Y. ,  SHIRAIWA, Hidehiko ,  VAN BUSKIRK, Michael, A. ,  ROGERS, David, M. ,  SUNKAVALLI, Ravi ,  WANG, Janet ,  DERHACOBIAN, Narbeh ,  WU, Yider

IPC: H01L27/115 ,  H01L21/8246

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573

Abstract: One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate (12); a charge trapping dielectric (14) over the core region of the substrate (12); a gate dielectric in the periphery region of the substrate (12); buried bitlines (26) under the charge trapping dielectric (14) in the core region; and wordlines (28) over the charge trapping dielectric (14) in the core region, wherein the core region is substantially planar. Another aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving sequentially or non-sequentially forming a charge trapping dielectric (14) over a substrate (12); removing at least a portion of the charge trapping dielectric (14) in the periphery region (18); forming a gate dielectric (22) in the periphery region (18); forming buried bitlines (26) in the core region (16); and forming gates (28) in the core region (16) and the periphery region (18).

公开(公告)号：EP1709682A1

公开(公告)日：2006-10-11

申请号：EP04814984.3

申请日：2004-12-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： LINGUNIS, Emmanuil, H. ,  WONG, Nga-Ching, Alan ,  HADDAD, Sameer ,  RANDOLPH, Mark, W. ,  RAMSBEY, Mark, T. ,  MELIK-MARTIROSIAN, Ashot ,  RUNNION, Edward, F. ,  HE, Yi

IPC: H01L21/8246 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/792 ,  H01L29/10

CPC classification number: H01L27/11568 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/1083 ,  H01L29/66833 ,  Y10S438/959

Abstract: A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer (608) is formed over a substrate (602) and a resist (614) is formed over the portion of the charge trapping dielectric layer (608). The resist (614) is patterned and a pocket implant (630) is performed at an angle to establish pocket implants (620) within the substrate (602). A bitline implant (634) is then performed to establish buried bitlines (640) within the substrate (602). The patterned resist is then removed and the remainder of the charge trapping dielectric layer (608) is formed. A wordline material (660) is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines (662) that overlie the bitlines (640). The pocket implants (620) serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.