公开(公告)号：WO2012138509A3

公开(公告)日：2013-01-03

申请号：PCT/US2012030753

申请日：2012-03-27

Applicant: ALTERA CORP ,  DING WEIQI ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  HOANG TIM TRI ,  KE YANJING

Inventor： DING WEIQI ,  SHUMARAYEV SERGEY ,  WONG WILSON ,  HOANG TIM TRI ,  KE YANJING

IPC: H04B1/04 ,  H03L7/00

CPC classification number: H03K5/1565 ,  H03K3/017 ,  H03K5/12 ,  H03M9/00

Abstract: A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples.

Abstract translation: 发射机电路可操作以响应于第一周期性信号提供输出信号。 多路复用器电路可操作以在第一操作阶段期间提供作为选定信号的第二周期信号。 多路复用器电路可操作以在第二操作阶段期间将发射机电路的输出信号提供为所选择的信号。 采样器电路可操作以在第一操作阶段产生所选信号的第一采样。 采样器电路可操作以在第二操作阶段期间产生所选信号的第二采样。 占空比控制电路可操作以基于第一和第二采样来调整第一周期信号的占空比。

公开(公告)号：WO2012037517A2

公开(公告)日：2012-03-22

申请号：PCT/US2011052028

申请日：2011-09-16

Applicant: ALTERA CORP ,  DING WEIQI ,  PAN MINGDE ,  LI PENG ,  SHUMARAYEV SERGEY ,  SHIMANOUCHI MASASHI

Inventor： DING WEIQI ,  PAN MINGDE ,  LI PENG ,  SHUMARAYEV SERGEY ,  SHIMANOUCHI MASASHI

IPC: H04L1/00 ,  G01R29/02

CPC classification number: H04L1/203 ,  G01R31/3171

Abstract: An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.

Abstract translation: 提供了一种IC，其包括耦合到眼睛观察者的眼睛观察器和BER检查器，其中BER检查器从眼睛观察器接收串行数据信号。 在一个实现中，BER检查器从眼睛观察器接收串行数据信号，而不经过串行数据信号通过解串器。 在一个实现中，BER检验器将串行数据信号与参考数据信号进行比较，以确定串行数据信号的BER。 在一个实现中，IC包括耦合到眼睛观察器和BER检查器的IC核心，其中BER检验器在IC核心之外。 在一个实现中，BER检查器是专用的BER检查器。 在一个实现中，BER检查器包括异或门，耦合到异或门的可编程延迟电路和耦合到异或门的错误计数器。

公开(公告)号：WO2010051244A2

公开(公告)日：2010-05-06

申请号：PCT/US2009062028

申请日：2009-10-26

Applicant: ALTERA CORP ,  WONG WILSON ,  CHAN ALLEN ,  SHUMARAYEV SERGEY

Inventor： WONG WILSON ,  CHAN ALLEN ,  SHUMARAYEV SERGEY

IPC: G01R31/28 ,  H03M1/12

CPC classification number: G01R31/3167

Abstract: An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.

Abstract translation: 介绍了一种能够监测模拟模块内部模拟电压的集成电路。 该集成电路有一个模拟测试多路复用器（mux），其输入端连接到模拟模块内部感兴趣的模拟电压。 模拟测试多路复用器将选定的模拟电压从模拟模块引导至模拟测试多路复用器的输出。 该集成电路还包括模拟监视状态机，其向模拟测试多路复用器提供选择位，使得能够随机访问模拟块内的模拟电压。 集成电路还包括模数转换器，用于将来自模拟测试多路复用器的选定模拟电压转换为数字表示。

公开(公告)号：WO2010033436A2

公开(公告)日：2010-03-25

申请号：PCT/US2009056753

申请日：2009-09-11

Applicant: ALTERA CORP ,  HOANG TIM TRI ,  WONG WILSON ,  SHUMARAYEV SERGEY

Inventor： HOANG TIM TRI ,  WONG WILSON ,  SHUMARAYEV SERGEY

IPC: H03L7/193 ,  H03L7/087

CPC classification number: H03L7/099 ,  H03L7/18

Abstract: A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals.

Abstract translation: 一种电路包括相位检测电路，时钟信号生成电路，第一分频器和第二分频器。 相位检测电路将输入时钟信号与反馈信号进行比较以生成控制信号。 时钟信号产生电路响应于控制信号产生周期性输出信号。 第一分频器将周期性输出信号的频率除以第一值以产生第一分频信号。 第二分频器将周期性输出信号的频率除以第二值以产生第二分频信号。 第一和第二分频信号在不同的时间间隔期间作为反馈信号被路由到相位检测电路。

公开(公告)号：WO0052825A9

公开(公告)日：2001-11-29

申请号：PCT/US0005488

申请日：2000-03-02

Applicant: ALTERA CORP

Inventor： SCHLEICHER JAMES ,  PARK JIM ,  SHUMARAYEV SERGEY ,  PEDERSON BRUCE ,  NGAI TONY ,  HUANG WEI-JEN ,  MARURI VICTOR ,  PATEL RAKESH

IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177

CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

Abstract translation: 可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。 此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。 本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。 由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

公开(公告)号：WO0052826A2

公开(公告)日：2000-09-08

申请号：PCT/US0005628

申请日：2000-03-02

Applicant: ALTERA CORP

Inventor： NGAI TONY ,  PEDERSON BRUCE ,  SHUMARAYEV SERGEY ,  SCHLEICHER JAMES ,  HUANG WEI-JEN ,  HUTTON MICHAEL ,  MARURI VICTOR ,  PATEL RAKESH ,  KAZARIAN PETER J ,  LEAVER ANDREW ,  MENDEL DAVID W ,  PARK JIM

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17744

Abstract: A programmable logic integrated circuit device (10) has a plurality of regions (20) of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

Abstract translation: 可编程逻辑集成电路器件（10）具有多个可编程逻辑区域（20），该可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间和/或之间进行可编程互连。 这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。 例如，这种双形互连资源（200a，210a，230a）的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分（200b，210b，230b）可具有明显更快的信号速度 。 辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

公开(公告)号：DE602006019184D1

公开(公告)日：2011-02-10

申请号：DE602006019184

申请日：2006-08-25

Applicant: ALTERA CORP

Inventor： LAI TIN ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  WONG WILSON

IPC: H03G3/20 ,  H04L25/03

公开(公告)号：GB2351824B

公开(公告)日：2004-03-31

申请号：GB0016223

申请日：2000-06-30

Applicant: ALTERA CORP

Inventor： NGAI TONY ,  SHUMARAYEV SERGEY ,  HUANG WEI-JEN ,  PATEL RAKESH H ,  LAI TIN

IPC: G11C5/02 ,  H03K19/177

Abstract: A high-performance programmable logic architecture has embedded memory (608). arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements (805) can be directly programmable routed and connected to driver blocks (809) of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources (815, 825). Using similar direct programmable interconnections (828, 830, 835), the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.

公开(公告)号：AT493793T

公开(公告)日：2011-01-15

申请号：AT06017779

申请日：2006-08-25

Applicant: ALTERA CORP

Inventor： LAI TIN ,  SHUMARAYEV SERGEY ,  MAANGAT SIMARDEEP ,  WONG WILSON

IPC: H03G3/20 ,  H04L25/03

Abstract: Equalization circuitry may be used to compensate for the attenuation of a data signal caused by a transmission medium. The control circuitry for the equalization circuitry may generate control inputs for equalization stages that control the amount of gain provided to the data signal. A comparator may determine whether the gain from the equalization circuitry is less than or more than the desired amount of gain. A programmable up/down counter may adjust the counter value based on the output of the comparator. The counter value may be converted into one or more analog voltages using one or more digital-to-analog converters. These analog voltages may be provided to the equalization stages as control inputs. The control circuitry may also include hysteresis circuitry that prevents the counter value from being adjusted when the gain produced by the equalization stages is close to the desired amount of gain.

公开(公告)号：DE60044311D1

公开(公告)日：2010-06-10

申请号：DE60044311

申请日：2000-07-14

Applicant: ALTERA CORP

Inventor： SHUMARAYEV SERGEY ,  HUANG WEI-JEN ,  PATEL RAKESH

IPC: H01L27/04 ,  H03K19/177 ,  G06F7/38 ,  H01L21/82 ,  H01L21/822 ,  H01L25/00 ,  H01L27/02 ,  H01L27/118 ,  H05K3/40 ,  H05K7/02

Abstract: A programmable logic device package comprising: a package (64); a solder ball (66) positioned on a first surface of said package, said solder ball located for receiving an external signal, a plurality of signal interface bumps (62) positioned on a second surface of the package, and a set of routing leads (68) extending through said package and connecting said solder ball to each of the plurality of signal interface bumps, wherein said set of routing leads distribute said external signal to said signal interface bumps.