公开(公告)号：GB2308250A

公开(公告)日：1997-06-18

申请号：GB9622934

申请日：1996-11-04

Applicant: ALTERA CORP

Inventor： TURNER JOHN E ,  NOUBAN BEHZAD

IPC: H03K5/00 ,  H03K5/159 ,  H03L7/081 ,  H03L7/16

公开(公告)号：JPH10334678A

公开(公告)日：1998-12-18

申请号：JP6997098

申请日：1998-03-19

Applicant: ALTERA CORP

Inventor： MADURAWE RAMINDA U ,  SMOLEN RICHARD G ,  LIANG MINCHANG ,  SANSBURY JAMES D ,  TURNER JOHN E ,  COSTELLO JOHN C ,  WONG MYRON W

IPC: G11C16/04 ,  G11C16/26 ,  G11C29/50 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a biasing method of a dual low line EEPROM to reduce stress on the dielectric material window of cell. SOLUTION: A bias voltage is applied to the control gate 40 and floating gate 32 of the EEPROM cell 200 to result in a potential difference between the control gate voltage and floating gate voltage of about 0.5 V or less. A tunnel oxidization film area is remarkably reduced by biasing the control voltage and floating gate voltage of cell 200. Moreover, a write column voltage is selected on the basis of the control gate voltage to substantially keep the balance of the tunnel oxidization film area in all operation modes.

公开(公告)号：GB2312068B

公开(公告)日：2000-03-29

申请号：GB9707323

申请日：1997-04-10

Applicant: ALTERA CORP

Inventor： PASS CHRISTOPHER J ,  SANSBURY JAMES D ,  MADURAWE RAMINDA U ,  TURNER JOHN E ,  PATEL RAKESH H ,  WRIGHT PETER J

IPC: H03K19/177 ,  H03K19/0175

Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.

公开(公告)号：DE69223379D1

公开(公告)日：1998-01-15

申请号：DE69223379

申请日：1992-09-09

Applicant: ALTERA CORP

Inventor： TURNER JOHN E

IPC: G11C16/02 ,  G11C16/04 ,  G11C17/00 ,  G11C16/14 ,  G11C16/16 ,  H03K19/173 ,  H03K19/177 ,  G11C16/06

Abstract: A method and apparatus for erasing Flash EPROM cells that avoids overerasure is provided. A high-impedance device is placed between the drain of the cell and the high-voltage supply used to erase the cell. As soon as the cell enters the onset of depletion and begins to conduct, most of the high voltage is dropped across the high-impedance device, leaving insufficient potential across the cell for Fowler-Nordheim tunneling to continue. The erase process is thus self-limiting. The process can be used on a chain or array of EPROM cells, with erasure stopping when any one of the cells conducts. Bias differences between erase and read modes assure that the cell that first goes into depletion is not in depletion in normal operation.