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    Semiconductor structure capturing impurity oxygen for high-k gate dielectric, and method for forming the structure (capture metal stack for high-k gate dielectric)
    13.
    发明专利
    Semiconductor structure capturing impurity oxygen for high-k gate dielectric, and method for forming the structure (capture metal stack for high-k gate dielectric) 有权
    用于高K栅介质的半导体结构捕获强度氧化物和形成结构的方法（用于高K栅介质的捕获金属堆叠）

    公开(公告)号：JP2011003899A

    公开(公告)日：2011-01-06

    申请号：JP2010136861

    申请日：2010-06-16

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： ANDO TAKASHI ,  CHOI CHANGHWAN ,  NARAYANAN VIJAY ,  FRANK MARTIN M

    IPC: H01L29/78 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

    CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

    Abstract: PROBLEM TO BE SOLVED: To provide a high-k gate dielectric which maintains a constant threshold voltage even after a high temperature process in a CMOS integration step.SOLUTION: A stack of a high-k gate dielectric 30 and a metal gate structure including a lower metal layer 40, a capture metal layer 50, and an upper metal layer 60 is provided. The capture metal layer satisfies the following two standards: (1) to be a metal (M) which indicates a positive change in Gibbs free energy caused by a reaction of Si+2/yMO→2x/yM+SiO; and (2) to be a metal the Gibbs free energy of which is a larger negative value than a metal of the lower metal layer and a metal of the upper metal layer per oxygen atom to form an oxide. The capture metal layer satisfying these standards captures oxide atoms when the oxide atoms pass through a gate electrode, to be diffused toward the high-k gate dielectric. Furthermore, the capture metal layer reduces a thickness of a silicon oxide interface layer under the high-k gate dielectric remotely. As a result, a change in equivalent oxide thickness (EOT) of the whole gate dielectric is controlled.

    Abstract translation: 要解决的问题：提供即使在CMOS集成步骤中的高温处理之后仍保持恒定的阈值电压的高k栅极电介质。解决方案：高k栅极电介质30和金属栅极结构的堆叠包括 提供下金属层40，捕获金属层50和上金属层60。 捕获金属层满足以下两个标准：（1）作为表示由Si + 2 / yMO→2x / yM + SiO的反应引起的吉布斯自由能的正变化的金属（M） 和（2）作为金属，其吉布斯自由能比下金属层的金属和每个氧原子的上金属层的金属具有更大的负值，以形成氧化物。 当氧化物原子通过栅电极时，满足这些标准的捕获金属层捕获氧化物原子，以朝向高k栅极电介质扩散。 此外，捕获金属层远离了高k栅极电介质下的氧化硅界面层的厚度。 结果，控制了整个栅极电介质的等效氧化物厚度（EOT）的变化。

    Semiconductor/dielectric/semiconductor device structure manufactured by wafer bonding
    15.
    发明专利
    Semiconductor/dielectric/semiconductor device structure manufactured by wafer bonding 有权
    半导体/电介质/半导体器件结构由波形焊接制造

    公开(公告)号：JP2006054465A

    公开(公告)日：2006-02-23

    申请号：JP2005233104

    申请日：2005-08-11

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： FRANK MARTIN M ,  REZNICEK ALEXANDER ,  GOUSEV EVGENI P ,  CARTIER EDUARD A

    IPC: H01L29/78 ,  H01L21/02 ,  H01L21/283

    CPC classification number: H01L29/495 ,  H01L21/76254 ,  H01L21/823828 ,  H01L29/517

    Abstract: PROBLEM TO BE SOLVED: To provide a technique for forming a gate stack partially at least on a semiconductor substrate which makes it possible to use various gate materials without sacrificing device performance.
    SOLUTION: There is provided the method of forming a gate stack for a semiconductor electron device using the wafer bonding of at least one structure containing a high k dielectric material. The method comprises a step of selecting first and second structures each having a principal plane. At least one of or both of the first and the second structures comprise the high k dielectric material at least. Then, a bonding structure comprising at least the high k dielectric material of the gate stack is formed by joining the primary planes of the first and the second structures.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供至少部分地在半导体衬底上形成栅叠层的技术，这使得可以在不牺牲器件性能的情况下使用各种栅极材料。 解决方案：提供了使用包含高k电介质材料的至少一种结构的晶片接合形成半导体电子器件的栅极堆叠的方法。 该方法包括选择具有主平面的第一和第二结构的步骤。 第一和第二结构中的至少一个或两者至少包括高k电介质材料。 然后，通过连接第一和第二结构的主平面来形成至少包括栅叠层的高k电介质材料的键合结构。 版权所有（C）2006，JPO＆NCIPI

    Controlling ferroelectricity in dielectric films by process induced uniaxial strain
    18.
    发明专利
    Controlling ferroelectricity in dielectric films by process induced uniaxial strain 未知

    公开(公告)号：GB2492697A

    公开(公告)日：2013-01-09

    申请号：GB201218702

    申请日：2011-03-15

    Applicant: IBM

    Inventor： DUBOURDIEU CATHERINE A ,  FRANK MARTIN M

    IPC: H01L21/28 ,  H01L27/20 ,  H01L29/66 ,  H01L29/78 ,  H01L41/09

    Abstract: A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.

    19.
    发明专利
    未知

    公开(公告)号：AT526684T

    公开(公告)日：2011-10-15

    申请号：AT05826298

    申请日：2005-12-02

    Applicant: IBM

    Inventor： CALLEGARI ALESSANDRO C ,  FRANK MARTIN M ,  JAMMY RAJARAO ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  ZAFAR SUFI

    IPC: H01L27/088 ,  H01L21/28 ,  H01L29/49

    Abstract: A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

    Niedrige Schwellenspannung und Skalierung der Inversionsoxiddicke für einen Mosfet vom P-Typ mit High-K-Metall-Gate
    20.
    发明专利
    Niedrige Schwellenspannung und Skalierung der Inversionsoxiddicke für einen Mosfet vom P-Typ mit High-K-Metall-Gate 未知

    公开(公告)号：DE112012002543T5

    公开(公告)日：2014-05-22

    申请号：DE112012002543

    申请日：2012-07-30

    Applicant: IBM

    Inventor： ANDO TAKASHI ,  KWON UNOH ,  CHOI CHANGHWAN ,  FRANK MARTIN M ,  NARAYANAN VIJAY

    IPC: H01L29/00

    Abstract: Eine Struktur weist ein Halbleitersubstrat (8) und einen nFET und einen pFET auf, die auf dem Substrat (8) angeordnet sind. Der pFET weist ein SiGe-Kanalgebiet auf, das auf oder in einer Fläche des Halbleitersubstrats (8) gebildet ist, und ein Gate-Dielektrikum mit einer Oxidschicht (20), die über dem Kanalgebiet liegt, und eine dielektrische High-k-Schicht (30), die über der Oxidschicht (20) liegt. Eine Gate-Elektrode liegt über dem Gate-Dielektrikum und weist eine untere Metallschicht (40), die an die High-k-Schicht angrenzt, eine adsorbierende Metallschicht (50), die an die untere Metallschicht (40) angrenzt, und eine obere Metallschicht (60) auf, die an die adsorbierende Metallschicht (50) angrenzt. Die Metallschicht adsorbiert Sauerstoff aus der Substrat (8)-(nFET) und SiGe-Grenzfläche (pFET) zur Oxidschicht (20), was zu einer effektiven Verringerung in Tinv und Vt des pFET führt, während Tinv skaliert wird und Vt für den nFET aufrechterhalten wird, was zur Folge hat, dass die Vt des pFET näher an der Vt eines ähnlich aufgebauten nFET mit skalierten Tinv-Werten liegt.

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