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    11.
    发明专利
    未知

    公开(公告)号：DE69331052D1

    公开(公告)日：2001-12-06

    申请号：DE69331052

    申请日：1993-07-01

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： ZAMBRANO RAFFAELE ,  LEONARDI SALVATORE ,  CACCIOLA GIOVANNA

    IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L29/06 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78 ,  H01L21/329 ,  H01L21/336 ,  H01L21/761

    Abstract: An integrated edge structure for a high voltage semiconductor device comprising a PN junction represented by a diffused region (3,7) of a first conductivity type extending from a semiconductor device top surface is described. The edge structure comprises a first lightly doped ring (4) of the first conductivity type obtained in a first lightly doped epitaxial layer (2) of a second conductivity type and surrounding said diffused region (3,7), and a second lightly doped ring (8) of the first conductivity type, superimposed on and merged with said first ring (4), obtained in a second lightly doped epitaxial layer (6) of the second conductivity type grown over the first epitaxial layer (2).

    14.
    发明专利
    未知

    公开(公告)号：DE69325645D1

    公开(公告)日：1999-08-19

    申请号：DE69325645

    申请日：1993-04-21

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： ZAMBRANO RAFFAELE

    IPC: H01L29/78 ,  H01L27/02 ,  H01L27/04

    Abstract: An integrated structure protection device suitable for protecting a power MOS device from electro static discharges comprises a junction diode (9) comprising a first electrode made of a highly doped region (12) of a first conductivity type surrounded by a body region (11) of a second conductivity type and representing a second electrode of the junction diode (9), which in turn is surrounded by a highly doped deep body region (10) of said second conductivity type. The highly doped region (12) is connected to a polysilicon gate layer (7) representing the gate of the power MOS device, while the deep body region (10) is connected to a source region (6) of the power MOS.

    15.
    发明专利
    未知

    公开(公告)号：DE69131390D1

    公开(公告)日：1999-08-05

    申请号：DE69131390

    申请日：1991-04-11

    Applicant: CONS RIC MICROELETTRONICA

    Inventor： ZAMBRANO RAFFAELE

    IPC: H01L21/336 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06

    Abstract: The invention relates to a process for forming a buried drain or collector region in monolithic semiconductor devices comprising an integrated control circuit and one or more power transistors with vertical current flow integrated in the same chip. The process allows optimization of the current-carrying capacity and the series drain resistance of the power stage and operating voltage in comparison with known structures by provision of one or more regions of high dopant concentration defined after growth of a first epitaxial layer.

    17.
    发明专利
    未知

    公开(公告)号：DE69122598T2

    公开(公告)日：1997-03-06

    申请号：DE69122598

    申请日：1991-12-18

    Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

    Inventor： PUZZOLO SANTO ,  ZAMBRANO RAFFAELE ,  PAPARO MARIO

    IPC: H01L21/8249 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L21/82

    Abstract: In the version with unisolated components the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer; the low voltage bipolar transistor is indeed situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In the version with isolated components, in an n- epitaxial layer there are two p+ regions, i.e. the first, constituting the power transistor base, encloses the n+ emitter region of said transistor while the second encloses two n+ regions and one p+ region constituting the collector, emitter and base regions respectively of the low voltage transistor. A metallization on the front of the chip provides connection between the collector contact of the low voltage transistor and the emitter contact of the power transistor.

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