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    11.
    发明专利
    未知

    公开(公告)号：DE69012954D1

    公开(公告)日：1994-11-03

    申请号：DE69012954

    申请日：1990-10-09

    Applicant: IBM

    Inventor： BORKENHAGEN JOHN MICHAEL ,  DOUSKEY STEVEN MICHAEL ,  MEYER JEROME MARTIN

    IPC: G01R31/28 ,  G01R31/00 ,  G06F11/16 ,  G06F11/22 ,  G06F11/267 ,  G01R31/318

    Abstract: A method and apparatus for identifying stuck faults in an oscillator used for providing a oscillator input signal (12) to an integrated circuit chip of the type conforming to a Level Sensitive Scan Design (LSSD) system and testing technique. A pair of shift register latches (SRLs) (20,30) are provided in the integrated circuit chip having a logical one signal applied to a data input of the SRLs. The oscillator input signal is applied to a data clock input of a first one (20) of the SRLs and an inverted oscillator input signal is applied to the data clock input of a second one (30) of the SRLs. Then the scan data output (SDO) of the test SRLs is detected responsive to the applied oscillator and inverted oscillator input signals to identify a stuck fault.

    Verwalten von komprimiertem Speicher unter Verwendung gestaffelter Interrupts
    12.
    发明专利
    Verwalten von komprimiertem Speicher unter Verwendung gestaffelter Interrupts 未知

    公开(公告)号：DE112011103408T5

    公开(公告)日：2013-10-31

    申请号：DE112011103408

    申请日：2011-09-23

    Applicant: IBM

    Inventor： POFF DAN ,  BORKENHAGEN JOHN MICHAEL ,  ABALI BULENT

    IPC: G06F9/48 ,  G06F12/02 ,  G06F12/08

    Abstract: Es werden Systeme und Verfahren zum Verwalten von Speicher bereitgestellt. Ein bestimmtes Verfahren kann das Auslösen einer Speicherkomprimierungsoperation beinhalten. Das Verfahren kann ferner das Auslösen eines ersten Interrupts beinhalten, der so konfiguriert ist, dass er als Reaktion auf eine erste erkannte Speicherstufe einen ersten Prozess beeinflusst, der auf einem Prozessor ausgeführt wird. Ein zweiter ausgelöster Interrupt kann so konfiguriert sein, dass er als Reaktion auf eine zweite erkannte Speicherstufe den ersten Prozess beeinflusst, der auf dem Prozessor ausgeführt wird, und ein dritter Interrupt kann ausgelöst werden, damit er als Reaktion auf eine dritte erkannte Speicherstufe den ersten Prozess beeinflusst, der auf dem Prozessor ausgeführt wird. Es wird zumindest die erste, die zweite oder die dritte Speicherstufe durch die Speicherkomprimierungsoperation beeinflusst.

    Managing compressed memory using tiered interrupts
    13.
    发明专利
    Managing compressed memory using tiered interrupts 未知

    公开(公告)号：GB2500834A

    公开(公告)日：2013-10-02

    申请号：GB201310842

    申请日：2011-09-23

    Applicant: IBM

    Inventor： BORKENHAGEN JOHN MICHAEL ,  ABALI BULENT ,  POFF DAN

    IPC: G06F12/02 ,  G06F12/08 ,  G06F13/24

    Abstract: Systems and methods to manage memory are provided. A particular method may include initiating a memory compression operation. The method may further include initiating a first interrupt configured to affect a first process executing on a processor in response to a first detected memory level. A second initiated interrupt may be configured to affect the first process executing on the processor in response to a second detected memory level, and a third interrupt may be initiated to affect the first process executing on the processor in response to a third detected memory level. At least of the first, the second, and the third detected memory levels are affected by the memory compression operation.

    18.
    发明专利
    未知

    公开(公告)号：DE602004007681D1

    公开(公告)日：2007-08-30

    申请号：DE602004007681

    申请日：2004-09-10

    Applicant: IBM

    Inventor： BORKENHAGEN JOHN MICHAEL ,  ZUMBRUNNEN LAURA MARIE

    IPC: G06F11/20 ,  G06F11/00 ,  H04L12/26 ,  H04L12/40

    Abstract: Methods and apparatus are provided that allow an electronic system having a signaling bus with a fault on a signaling conductor to operate at a degraded performance. A block of data is transferred from a first electronic unit to a second electronic unit over the signaling bus. A transmission sequence sends the block of data using all of the nonfaulty signaling conductors using a minimum number of beats required to complete the transmission.

    METHOD AND APPARATUS FOR SELECTING THREAD SWITCH EVENTS IN AMULTITHREADED PROCESSOR
    19.
    发明专利
    METHOD AND APPARATUS FOR SELECTING THREAD SWITCH EVENTS IN AMULTITHREADED PROCESSOR 未知

    公开(公告)号：CA2299348A1

    公开(公告)日：1999-04-29

    申请号：CA2299348

    申请日：1998-10-14

    Applicant: IBM

    Inventor： WOTTRENG ANDREW HENRY ,  BORKENHAGEN JOHN MICHAEL ,  EICKEMEYER RICHARD JAMES ,  FLYNN WILLIAM THOMAS

    IPC: G06F12/08 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

    Abstract: A system and method for performing computer processing operations in a data processing system (10) includes a multithreaded processor (100) and thread switch logic (400). The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register (440) depending on its execution status. The thread switch logic contains a thread switch control register (410) to store the conditions upon which a thread will occur. The thread switch logic has a time-out register (430) which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register (420) to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager (460) capable of changing the priority of the different threads and thus superseding thread switch events.

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