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公开(公告)号：DE69914966D1
公开(公告)日：2004-04-01
申请号：DE69914966
申请日：1999-04-19
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , MCLAUGHLIN CHARLES ANDREW , NEAL DANNY MARVIN , NICHOLSON JAMES OTTO , THURBER STEVEN MARK
Abstract: Device selects lines 202n from each I/O device 132 are brought into a PCI host bridge 124 individually so that the device number of a failing device may be logged in an error register 204 when an error is seen on the PCI bus. Until the error register is reset, subsequent load and store operations are delayed until the device number of the subject device may be checked against the error register. If the subject device is a previously failing device, the load/store operation to that device is prevented from completing, either by forcing bad parity or zeroing all byte enables. By forcing bad parity or zero byte enables, the I/O device will respond to the load or store request by activating its device select line, but will not accept store data. Operations to devices which are not logged in the error register are permitted to proceed normally, as are all load store operations when the error register is clear. Normal system operations are thus not impacted, and operations during error recovery are permitted to proceed if no further damage will be caused by such operations.
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公开(公告)号：DE69127416T2
公开(公告)日：1998-02-26
申请号：DE69127416
申请日：1991-06-21
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , HSIAO MU-YUE , MULLIGAN JAMES MICHAEL
Abstract: A single width bidirectional bar code exhibiting inherent self clocking characteristics is provided so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described herein are robust, reliable and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear measurements, an important consideration in semiconductor manufacturing wherein space on chips and wafers is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.
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公开(公告)号：NZ232458A
公开(公告)日：1992-03-26
申请号：NZ23245890
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：AU615373B2
公开(公告)日：1991-09-26
申请号：AU4939990
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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15.发明专利
公开(公告)号：DE3068895D1
公开(公告)日：1984-09-13
申请号：DE3068895
申请日：1980-10-29
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG
Abstract: The output of a data storage array is gated into an error correcting code based syndrome generator (18) and a register (16), the syndrome being gated into an associative store (20) holding all connectable syndromes and a "no-error" syndrome with search field and bit locators in its result field. Hit and miss signals pass to gating control (22) which respond to a miss (NC) to gate, sequentially, test patterns from a store (30) into the above and back to the syndrome generator. If, at the end of the tests a specific number of errors are identified which number lies in the correcting capability of the code, an identifier syndrome is copied from the search field of the store (20) into register (32) and the syndromes in (28) and (32) are XORed at (34) and used to interrogate the store (20). The error locations from (20) for the test syndrome and the output of (34), (if any) are used by inverter controls (26) to correct the data in (16).
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Patent Agency Ranking
公开(公告)号：DE2357233A1
公开(公告)日：1974-06-20
申请号：DE2357233
申请日：1973-11-16
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , HAUGH CONNOR FRANCIS , HSIAO MU-YUE
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公开(公告)号：DE60040382D1
公开(公告)日：2008-11-13
申请号：DE60040382
申请日：2000-12-22
Applicant: IBM
Inventor： BARNETT BARRY STANLEY , BOSSEN DOUGLAS CRAIG
IPC: G06F13/10 , H04L12/24 , G06F13/00 , G06F15/177
Abstract: A method and system for problem determination and fault isolation in a storage area network (SAN) is provided. A complex configuration of multi-vendor host systems, FC switches, and storage peripherals are connected in a SAN via a communications architecture (CA). A communications architecture element (CAE) is a network-connected device that has successfully registered with a communications architecture manager (CAM) on a host computer via a network service protocol, and the CAM contains problem determination (PD) functionality for the SAN and maintains a SAN PD information table (SPDIT). The CA comprises all network-connected elements capable of communicating information stored in the SPDIT. The CAM uses a SAN topology map and the SPDIT are used to create a SAN diagnostic table (SDT). A failing component in a particular device may generate errors that cause devices along the same network connection path to generate errors. As the CAM receives error packets or error messages, the errors are stored in the SDT, and each error is analyzed by temporally and spatially comparing the error with other errors in the SDT. If a CAE is determined to be a candidate for generating the error, then the CAE is reported for replacement if possible.
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公开(公告)号：DE69021413T2
公开(公告)日：1996-03-21
申请号：DE69021413
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：DE69021413D1
公开(公告)日：1995-09-14
申请号：DE69021413
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：AU4939390A
公开(公告)日：1990-09-13
申请号：AU4939390
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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