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    13.
    发明专利
    未知

    公开(公告)号：DE1169167B

    公开(公告)日：1964-04-30

    申请号：DEJ0021592

    申请日：1962-04-11

    Applicant: IBM

    Inventor： ANNEY WILLIAM H MC ,  LANGE LAWRENCE K ,  GRUODIS ALGIRDAS J

    IPC: G06F7/50 ,  G06F7/501 ,  H03K19/10

    Abstract: 995,097. Transistor logic circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 28, 1962 [April 17, 1961], No. 11826/62. Heading H3T. [Also in Division G4] A switching circuit comprises a transistor 26, Fig. 1, having a negative resistance element 20 connected in its input circuit, the arrangement being such that with low or high voltage level input signals the element 20 is biased to high current values t 1 , t 3 , Fig. 2, and with an intermediate voltage level input signal it is biased to a low current value t 2 . The transistor 25 is switched to one state by the high current states, and to a second by the low current state. As described, the circuit forms a Full Adder in which transistors 26, 28 are both cut off when no input signals are present at A, B, C. Application of a signal to one input opens its associated gate 35-37, connecting the position supply 38, and the tunnel diode 20 conducts at operating point t 1 , Fig. 2, switching on transistor 26. Application of a second input moves the operating point of the tunnel diode to t 2 cutting transistor 26 off again and switching on transistor 28. With three inputs present, the operating point of the tunnel diode moves to t 3 and both transistors conduct. If the transistor 28 and constitutes a PARITY or EXCLUSIVE OR its associated resistors are omitted, the circuit circuit Fig. 4 (not shown).

    14.
    发明专利
    未知

    公开(公告)号：FR2337426A1

    公开(公告)日：1977-07-29

    申请号：FR7635301

    申请日：1976-11-19

    Applicant: IBM

    Inventor： BALYOZ JOHN ,  GRUODIS ALGIRDAS J ,  JEN TEH-SEN ,  MIKHAIL WADIE F

    IPC: H01L27/082 ,  H01L21/82 ,  H01L21/8226 ,  H01L23/528 ,  H01L27/10 ,  H01L27/118 ,  H03K19/084 ,  H03K19/088 ,  H03K19/091 ,  H01L21/72 ,  H01L27/04

    Abstract: An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region; to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor is a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction. For the most part, this conductor connects the second device with one of the conductors in the first set. The reference potential connections to each circuit are also made preferably by conductive channels running in the same direction. With respect to chip architecture, each logic circuit is of substantially identical identical geometric form and arranged in columnar arrays.

    HIGH-SPEED PROGRAMMABLE TIMING GENERATOR
    16.
    发明专利
    HIGH-SPEED PROGRAMMABLE TIMING GENERATOR 未知

    公开(公告)号：DE3477716D1

    公开(公告)日：1989-05-18

    申请号：DE3477716

    申请日：1984-07-03

    Applicant: IBM

    Inventor： CHANG YIHUA E ,  GRASSO LAWRENCE J ,  GRUODIS ALGIRDAS J ,  MORGAN CARROLL E

    IPC: G06F1/08 ,  H03K3/78 ,  H03K5/156 ,  H03K23/66 ,  H03K5/13

    Abstract: A high-speed programmable timing generator in which a continuously cycling binary count is compared with an input data word. Predetermined bits, starting from the highest- order end of the counter (24), can be selectively inhibited by an inhibit word (M) to effectively vary the cycle period of the counter. The digital word (D) with which the output of the counter is compared can be varied to set the reference phase of the output timing pulse stream. Further, fine delay adjustment (23) of the phase of the output timing pulse stream is effected by a controllable phase-locked loop (22).

    Negative resistance integrated circuit - has two MOS FET's with specified gate connections for switching nide change-over
    17.
    发明专利
    Negative resistance integrated circuit - has two MOS FET's with specified gate connections for switching nide change-over 未知

    公开(公告)号：FR2296311A1

    公开(公告)日：1976-07-23

    申请号：FR7536058

    申请日：1975-11-19

    Applicant: IBM

    Inventor： GRUODIS ALGIRDAS J

    IPC: H03K19/017 ,  H03K19/0948 ,  H03K19/08 ,  H03K5/12

    Abstract: The complementary metal-oxide-semiconductor technology is used to produce an integrated circuit with a negative resistance characteristic under voltage application to a given circuit region. A metal-oxide-semiconductor transistor of a first channel type has its gate connected to the switching nodes and its source-drain path in series with a load to operating voltage source. A second such transistor of opposite channel type has its source-drain path connecting the switching node to the operating voltage source terminal, coupled to the load. This second transistor gate is connected to the junction point of the load and the first transistor. Thus the application of a voltage to a given region at the switching node the source-drain path of the second transistor becomes conductive.

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