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    11.
    发明专利
    未知

    公开(公告)号：DE2655575A1

    公开(公告)日：1977-07-07

    申请号：DE2655575

    申请日：1976-12-08

    Applicant: IBM

    Inventor： BALYOZ JOHN ,  GRUODIS ALGIRDAS JOSEPH ,  JEN TEH-SEN ,  MIKHAIL WADIE FALTAS

    IPC: H01L27/082 ,  H01L21/82 ,  H01L21/8226 ,  H01L23/528 ,  H01L27/10 ,  H01L27/118 ,  H03K19/084 ,  H03K19/088 ,  H03K19/091 ,  H01L27/04

    Abstract: An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region; to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor is a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction. For the most part, this conductor connects the second device with one of the conductors in the first set. The reference potential connections to each circuit are also made preferably by conductive channels running in the same direction. With respect to chip architecture, each logic circuit is of substantially identical identical geometric form and arranged in columnar arrays.

    12.
    发明专利
    未知

    公开(公告)号：DE2352762A1

    公开(公告)日：1974-05-16

    申请号：DE2352762

    申请日：1973-10-20

    Applicant: IBM

    Inventor： CHANG CHI SHIH ,  JEN TEH-SEN

    IPC: H01L21/331 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/00 ,  H01L29/417 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/73 ,  H01L29/78 ,  H01L19/00

    Abstract: 1423183 Complentary field-effect transistors INTERNATIONAL BUSINESS MACHINES CORP 12 Sept 1973 [1 Nov 1972] 42856/73 Heading H1K In a complementary pair of field-effect transistors formed in a single semiconductor substate, each gate electrode comprises polycrystalline or amorphous silicon. doped with a P-type impurity and certain regions have specified impurity levels. In an embodiment, an N-type Si body 2 has a P-type pocket 8 formed therein (Fig. 1b) by ion implantation beneath a screening oxide layer 6. The screening layer 6 and the oxide layer 4 are removed and replaced by an overall oxide layer (10, Fig. 1c, not shown) causing drive-in of the P-type pocket 8. An N-type layer 12 of phosphorus is made by ion implantation after pocket 8 has been covered with photo-resist. The N- and the P-type regions (8, 12) are drivenin further by heating. A thick layer of oxide 14 is formed on the top surface and windows formed for the source, drain and other connections (Fig. le, not shown). A thin layer of oxide (16) is grown in the windows and overall covering (18) of silicon nitride formed followed by an overall covering (20) of polycrystalline silicon. The top of the silicon covering is oxidized and the oxide selectively removed then the silicon to leave the polycrystalline silicon gates 20 1 and 20 11 (Fig. 1g). Oxidation, photo-resist and etching techniques give a structure having uncovered areas which recieve boron by ion implantation to form P-type regions 23, 26, 28, the implantation also rendering the gates 20 1 , 20 11 P-type (Fig. 1j). An oxide film is provided over the gates and other P-type areas and subsequent steps provide diffused N-type zones (30, 32, 34, Fig. 1l, not shown). Two pairs of complementary field effect transistors may be made in a single substrate and connected to form a NAND gate (Figs. 2a, 2b and 3).

    HIGH DENSITY SEMICONDUCTOR CIRCUIT LAYOUT
    14.
    发明专利
    HIGH DENSITY SEMICONDUCTOR CIRCUIT LAYOUT 未知

    公开(公告)号：CA1064624A

    公开(公告)日：1979-10-16

    申请号：CA268098

    申请日：1976-12-17

    Applicant: IBM

    Inventor： BALYOZ JOHN ,  GRUODIS ALGIRDAS J ,  JEN TEH-SEN ,  MIKHAIL WADIE F

    IPC: H01L27/082 ,  H01L21/82 ,  H01L21/8226 ,  H01L23/528 ,  H01L27/10 ,  H01L27/118 ,  H03K19/084 ,  H03K19/088 ,  H03K19/091 ,  H01L23/48 ,  H01L29/44 ,  H01L29/52

    Abstract: HIGH DENSITY SEMICONDUCTOR CIRCUIT LAYOUT An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region; to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor is a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction. For the most part, this conductor connects the second device with one of the conductors in the first set. The reference potential connections to each circuit are also made preferably by conductive channels running in the same direction. With respect to chip architecture, each logic circuit is of substantially identical identical geometric form and arranged in columnar arrays.

    16.
    发明专利
    未知

    公开(公告)号：DE2253614A1

    公开(公告)日：1973-05-10

    申请号：DE2253614

    申请日：1972-11-02

    Applicant: IBM

    Inventor： DOO VEN YOUNG ,  HO IRVING TZE ,  JEN TEH-SEN

    IPC: G11C27/04 ,  G11C19/18 ,  H01L21/00 ,  H01L21/33 ,  H01L21/339 ,  H01L27/105 ,  H01L29/70 ,  H01L29/762 ,  G11C19/00

    Abstract: 1336301 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 17 Oct 1972 [3 Nov 1971] 47774/72 Heading H1K A capacitor structure forming part of a semiconductor device comprises a semi-conductor body, an insulating layer on a sufrace of the body, a layer of doped polycrystalline semiconductor material overlying the insulating layer, a second insulating layer on the layer of polycrystalline material and a layer of conductive material in ohmic contact with the semi-conductor body overlying the polycrystalline layer and separated therefrom by the second insulating layer, the semi-conductor body and conductive layer forming one electrode of the capacitor, the polycrystalline layer, the second electrode and the insulating layers the dielectric. As shown the device is a bucket brigade shift register wherein such capacitors are connected between the collector and base of an array of switching bipolar transistors (Figs. 1 and 2, not shown). The transistors, comprising collector 40, collector contact region 42, base 44 and emitter 46, are formed in epitaxial layer 36 on monocrystalline silicon substrate 34 after sub-collector diffusion 38 has been formed. The transistors are separated by isolation diffusions 48. Layer 36 is covered by insulating layer 50 comprising thermal SiO 2 or SiO 2 /Si 3 N 4 with apertures for emitter, base and collector contacts 16, 18, 14. Layer 52 of doped polycrystalline silicon is insulated from overlying conductive layer by thermal SiO 2 layer 54. The capacitance of the device is between extension (58) of collector terminal 14 (Fig. 3, not shown) and polycrystalline layer 52 and between. collector region 40 and layer 52, one layer being in electrical contact with base terminal 18 through opening (56) (Fig. 3, not shown) in layer 54. Preferably the base terminals extend alternatively in opposite directions to contactone of a pair of clock lines (Fig. 3, not shown), best illustrated by the prior art arrangement (Fig. 1, not shown). The various metal layers may be deposited aluminium. In an alternative construction the device uses field effect transistors (Figs. 4, 5, not shown).

    18.
    发明专利
    未知

    公开(公告)号：DE2132560A1

    公开(公告)日：1972-01-05

    申请号：DE2132560

    申请日：1971-06-30

    Applicant: IBM

    Inventor： TZE HO IRVING ,  EDWARD HOWELL PETER ,  JEN TEH-SEN

    IPC: G11C19/18 ,  G11C19/28 ,  G11C19/00

    Abstract: 1345604 Semi-conductor data storage cell INTERNATIONAL BUSINESS MACHINES CORP 27 May 1971 [30 June 1970] 17441/71 Heading H3T [Also in Division G4] A capacitor storage cell C28, C33, T44, T46 has its stored data refreshed or maintained by a transistor 50 cross-coupled with T46 (Fig. 1). C28 is charged by a pulse 16 (Fig. 1A) at terminal 14 via R22, D24 and line 26, and discharged or not by T44 if the data input 10 is high or low respectively, when a negative pulse 56 occurs at T44 emitter 30; then C33 is charged by pulse 32 at 30 via R36, D38 and discharged or not by T46 when a negative pulse 52 occurs at T46 emitter 14 depending upon the stored voltage on C28. To regenerate the information stored to allow for leakage, a similar cycle of pulses is applied at times t 5 -t 8 but instead of T44 discharging C28 in dependence on the input, T50 is biased by a pulse 50 at 58 to discharge C28 or not according to the already stored level on C33. The transistor 50 may be replaced by a cross-coupled pair (T128, 130, Fig. 2, not shown) and in this case stored, information is maintained merely by a constantly applied negative level - V at their commoned emitters (134). A shift register (Fig. 3, not shown) has a plurality of these cells (156-m) in each row (150-n).

    20.
    发明专利
    未知

    公开(公告)号：FR2337426A1

    公开(公告)日：1977-07-29

    申请号：FR7635301

    申请日：1976-11-19

    Applicant: IBM

    Inventor： BALYOZ JOHN ,  GRUODIS ALGIRDAS J ,  JEN TEH-SEN ,  MIKHAIL WADIE F

    IPC: H01L27/082 ,  H01L21/82 ,  H01L21/8226 ,  H01L23/528 ,  H01L27/10 ,  H01L27/118 ,  H03K19/084 ,  H03K19/088 ,  H03K19/091 ,  H01L21/72 ,  H01L27/04

    Abstract: An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region; to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor is a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction. For the most part, this conductor connects the second device with one of the conductors in the first set. The reference potential connections to each circuit are also made preferably by conductive channels running in the same direction. With respect to chip architecture, each logic circuit is of substantially identical identical geometric form and arranged in columnar arrays.

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