公开(公告)号：GB2321544B

公开(公告)日：2001-08-01

申请号：GB9724351

申请日：1997-11-19

Applicant: IBM

Inventor： KAHLE JAMES ALLAN ,  MALLICK SOUMMYA ,  MCDONALD ROBERT G

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/48

公开(公告)号：GB2502222A

公开(公告)日：2013-11-20

申请号：GB201314787

申请日：2012-02-20

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  LE HUNG QUI ,  NGUYEN DUNG QUOC ,  BROWN MARY DOUGLASS ,  KAHLE JAMES ALLAN ,  EISEN SUSAN ELIZABETH

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: A system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.

公开(公告)号：AT248399T

公开(公告)日：2003-09-15

申请号：AT01904215

申请日：2001-02-16

Applicant: IBM

Inventor： KAHLE JAMES ALLAN

IPC: G06F9/34 ,  G06F9/38

Abstract: A method, processor, and data processing system for enabling maximum instruction issue despite the presence of complex instructions that require multiple rename registers is disclosed. The method includes allocating a first rename register from a first reorder buffer for storing the contents of a first register affected by the complex instruction. A second rename register from a second reorder buffer is then allocated for storing the contents of a second register affected by the complex instruction. In an embodiment in which the first reorder buffer supports a maximum number of allocations per cycle, the allocation of the second register using the second reorder buffer prevents the complex instruction from requiring multiple allocation slots in the first reorder buffer. The method may further include issuing a second instruction that contains a dependency on a register that is allocated in the secondary reorder buffer. In one embodiment, reorder buffer information indicating the second instruction's dependence on a register allocated in the secondary reorder buffer is associated with the second instruction such that, when the second instruction is issued subsequently, the reorder buffer information is used to restrict the issue unit to checking only the secondary reorder buffer for dependencies.

公开(公告)号：DE69430973D1

公开(公告)日：2002-08-22

申请号：DE69430973

申请日：1994-09-08

Applicant: IBM

Inventor： KAHLE JAMES ALLAN

IPC: G06F9/312 ,  G06F9/38 ,  G06F12/08

Abstract: An information processing system 10 includes a processor 10 for processing instructions, a system memory 30, a cache memory 12, and a supplemental 26. In response to a first instruction, the supplemental memory stores first information from a system memory. In response to a second instruction, the cache memory stores second information from the supplemental memory if the first information includes the second information and from the system memory otherwise.

公开(公告)号：AT220810T

公开(公告)日：2002-08-15

申请号：AT94306614

申请日：1994-09-08

Applicant: IBM

Inventor： KAHLE JAMES ALLAN

IPC: G06F9/312 ,  G06F9/38 ,  G06F12/08

Abstract: An information processing system 10 includes a processor 10 for processing instructions, a system memory 30, a cache memory 12, and a supplemental 26. In response to a first instruction, the supplemental memory stores first information from a system memory. In response to a second instruction, the cache memory stores second information from the supplemental memory if the first information includes the second information and from the system memory otherwise.

公开(公告)号：HK1035946A1

公开(公告)日：2001-12-14

申请号：HK01106575

申请日：2001-09-18

Applicant: IBM

Inventor： KAHLE JAMES ALLAN

IPC: G06F9/38 ,  G06F20060101 ,  G06F9/30 ,  G06F12/08 ,  G06F

公开(公告)号：GB2321545A

公开(公告)日：1998-07-29

申请号：GB9724389

申请日：1997-11-19

Applicant: IBM

Inventor： KAHLE JAMES ALLAN ,  MALLICK SOUMMYA ,  MCDONALD ROBERT G

IPC: G06F9/44 ,  G06F9/48 ,  G06F9/38 ,  G06F9/45

Abstract: In constructing a program, each of a plurality of instructions are assigned to at least one of a plurality of threads. The plurality of threads include first, second, and third threads, where the third thread follows the first thread and precedes the second thread in a logical program order. A data structure associated with the first thread is then constructed. The data structure includes an indication that execution of the second thread is to be initiated prior to initiation of execution of the third thread, i.e. the logical program order is to be reversed. According to one embodiment, the indication within the data structure is a pointer that specifies a second data structure associated with the second thread.

公开(公告)号：CA2126120A1

公开(公告)日：1995-04-02

申请号：CA2126120

申请日：1994-06-17

Applicant: IBM

Inventor： KAHLE JAMES ALLAN

IPC: G06F9/312 ,  G06F9/38 ,  G06F12/08 ,  G06F13/20

Abstract: An information processing system 10 includes a processor 10 for processing instructions, a system memory 30, a cache memory 12, and a supplemental 26. In response to a first instruction, the supplemental memory stores first information from a system memory. In response to a second instruction, the cache memory stores second information from the supplemental memory if the first information includes the second information and from the system memory otherwise.

公开(公告)号：GB2502222B

公开(公告)日：2014-04-09

申请号：GB201314787

申请日：2012-02-20

Applicant: IBM

Inventor： ABERNATHY CHRISTOPHER MICHAEL ,  LE HUNG QUI ,  NGUYEN DUNG QUOC ,  BROWN MARY DOUGLASS ,  KAHLE JAMES ALLAN ,  EISEN SUSAN ELIZABETH

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: A system and process for managing thread execution includes providing two data register sets coupled to a processor and using, by the processor, the two register sets as first-level registers for thread execution. A portion of main memory or cache memory is assigned as second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing the threads. Data for the threads may be moved between the first-level registers and second-level registers for different modes of thread processing.

公开(公告)号：DE60320026T2

公开(公告)日：2009-05-14

申请号：DE60320026

申请日：2003-11-21

Applicant: IBM

Inventor： DAY MICHAEL NORMAN ,  HOFSTEE HARM PETER ,  JOHNS CHARLES RAY ,  KAHLE JAMES ALLAN ,  TRUONG THUONG QUANG ,  SHIPPY DAVID

IPC: G06F12/10 ,  G06F12/12

Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.