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    11.
    发明专利
    未知

    公开(公告)号：DE2611559A1

    公开(公告)日：1976-10-07

    申请号：DE2611559

    申请日：1976-03-18

    Applicant: IBM

    Inventor： KU SAN-MEI ,  PILLUS CHARLES ANTHONY ,  POPONIAK MICHAEL ROBERT ,  SCHWENKER ROBERT OTTO

    IPC: C30B31/22 ,  H01L21/22 ,  H01L21/265 ,  H01L21/761 ,  B01J17/36 ,  B01J17/34

    Abstract: In integrated circuit fabrication, a method is provided for simultaneously forming two regions of the same conductivity-type such as the base and isolation regions. In one embodiment, an epitaxial layer of one conductivity-type is formed on a substrate of opposite conductivity-type, after which dopant ions of the opposite conductivity-type are introduced into the epitaxial surface areas which are to provide the base and isolation regions, and in addition, the isolation regions are bombarded with non-dopant ions having a maximum atomic number of two, e.g., hydrogen or helium ion while the base regions are appropriately masked and remain umbombarded, said bombardment is carried out at temperatures below 300 DEG C, preferably room temperature. The bombardment is preferably carried out so that the non-dopant ions are implanted primarily in regions below the isolation regions. Next, the wafer is heated at a temperature at a range of from 600 DEG - 900 DEG C which is substantially below normal drive-in diffusion temperatures for unbombarded doped regions. The heating to be maintained for a period sufficient to drive-in diffuse the bombarded isolation regions through the epitaxial layer into contact with the substrate but is insufficient to drive-in the unbombarded base regions to such a depth.

    12.
    发明专利
    未知

    公开(公告)号：DE68922817T2

    公开(公告)日：1995-11-30

    申请号：DE68922817

    申请日：1989-09-26

    Applicant: IBM

    Inventor： CHU SHAO-FU SANFORD ,  KU SAN-MEI ,  LANGE RUSSELL C ,  SHEPARD JOSEPH FRANCIS ,  TSANG PAUL JA-MIN ,  WANG WEN-YUAN

    IPC: H01L21/331 ,  H01L21/60 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/73 ,  H01L21/82 ,  H01L21/033 ,  H01L21/285 ,  H01L21/76

    Abstract: A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall. In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls. The second contact is thus self-aligned with the first and second doped regions and the first device contact. The method of the present invention can be utilized to fabricate bipolar transistors, insulated gate transistors, and BICMOS logic including both types of transistors. It can further be used to fabricate any other type of semiconductor device which utilizes the self-aligned, closely spaced device regions and contacts of the present invention.

    16.
    发明专利
    未知

    公开(公告)号：DE68922817D1

    公开(公告)日：1995-06-29

    申请号：DE68922817

    申请日：1989-09-26

    Applicant: IBM

    Inventor： CHU SHAO-FU SANFORD ,  KU SAN-MEI ,  LANGE RUSSELL C ,  SHEPARD JOSEPH FRANCIS ,  TSANG PAUL JA-MIN ,  WANG WEN-YUAN

    IPC: H01L21/331 ,  H01L21/60 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/73 ,  H01L21/82 ,  H01L21/033 ,  H01L21/285 ,  H01L21/76

    Abstract: A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall. In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls. The second contact is thus self-aligned with the first and second doped regions and the first device contact. The method of the present invention can be utilized to fabricate bipolar transistors, insulated gate transistors, and BICMOS logic including both types of transistors. It can further be used to fabricate any other type of semiconductor device which utilizes the self-aligned, closely spaced device regions and contacts of the present invention.

    METHOD OF FORMING CONTACTS TO A SEMICONDUCTOR DEVICE
    17.
    发明专利
    METHOD OF FORMING CONTACTS TO A SEMICONDUCTOR DEVICE 未知

    公开(公告)号：CA2011235C

    公开(公告)日：1993-06-29

    申请号：CA2011235

    申请日：1990-03-01

    Applicant: IBM

    Inventor： KU SAN-MEI ,  PERRY KATHLEEN A

    IPC: H01L29/73 ,  H01L21/285 ,  H01L21/302 ,  H01L21/331 ,  H01L21/768 ,  H01L29/732 ,  H01L21/44

    Abstract: METHOD OF FORMING CONTACTS TO A SEMICONDUCTOR DEVICE of the Invention A method of forming semiconductor device contacts includes the steps of: providing a semiconductor substrate having at least two features thereon whereat it is desired to make electrical connections; forming a layer of etch stop material having a first etch characteristic over each of the features; forming a layer of dielectric material having a second etch characteristic over each of the features; simultaneously etching at least two vias through the layer of dielectric material using an etchant selective to the layer of dielectric material so as to substantially stop on the layer of etch stop material, the at least two vias including a via over each of the features; and extending the vias through the layer of etch stop material so as to expose the features for subsequent electrical connections.

    SEMICONDUCTOR DEVICES HAVING CLOSELY SPACED DEVICE REGIONS FORMED USING A SELF ALIGNING REVERSE IMAGE FABRICATION PROCESS
    18.
    发明专利
    SEMICONDUCTOR DEVICES HAVING CLOSELY SPACED DEVICE REGIONS FORMED USING A SELF ALIGNING REVERSE IMAGE FABRICATION PROCESS 未知

    公开(公告)号：CA1300764C

    公开(公告)日：1992-05-12

    申请号：CA602547

    申请日：1989-06-12

    Applicant: IBM

    Inventor： CHU SHAO-FU S ,  KU SAN-MEI ,  LANGE RUSSELL C ,  SHEPHARD JOSEPH F ,  TSANG PAUL JA-MIN ,  WANG WEN-YUAN

    IPC: H01L29/73 ,  H01L21/331 ,  H01L21/60 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/82 ,  H01L21/033 ,  H01L21/285

    Abstract: SEMICONDUCTOR DEVICES HAVING CLOSELY SPACED DEVICE REGIONS FORMED USING A SELF ALIGNING REVERSE IMAGE FABRICATION PROCESS A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall. In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls. The second contact is thus self-aligned with the first and second doped regions and the first device contact. The method of the present invention can be utilized to fabricate bipolar transistors, insulated gate transistors, and BICMOS logic including both types of transistors. It can further be used to fabricate any other type of semiconductor device which utilizes the self-aligned, closely spaced device regions and contacts of the present invention. FI9-87-029

    19.
    发明专利
    未知

    公开(公告)号：DE2727557A1

    公开(公告)日：1978-01-12

    申请号：DE2727557

    申请日：1977-06-18

    Applicant: IBM

    Inventor： DEINES JOHN LOUIS ,  KU SAN-MEI ,  POPONIAK MICHAEL ROBERT ,  TSANG PAUL JA-MIN

    IPC: C30B25/02 ,  C30B29/36 ,  H01L21/04 ,  H01L21/205 ,  H01L21/762 ,  H01L29/267 ,  H01L21/18

    Abstract: A method for forming monocrystalline silicon carbide on a silicon substrate by converting a portion of the monocrystalline silicon substrate into a porous silicon substance by anodic treatment carried out in an aqueous solution of hydrofluoric acid, heating the resultant substrate to a temperature in the range of 1050 DEG C to 1250 DEG C in an atmosphere that includes a hydrocarbon gas for a time sufficient to react the porous silicon and the gas, thereby forming a layer of monocrystalline silicon carbide on the silicon substrate.

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