公开(公告)号：DE3853162T2

公开(公告)日：1995-08-17

申请号：DE3853162

申请日：1988-12-23

Applicant: IBM

Inventor： BASSO CLAUDE ,  PAUPORTE ANDRE ,  LEBIZAY GERALD ,  POIRAUD CLEMENT ,  MUNIER JEAN-MARIE

IPC: G06F15/16 ,  G06F9/46 ,  G06F12/06 ,  G06F13/16 ,  G06F15/167 ,  G06F15/177

公开(公告)号：DE3780307T2

公开(公告)日：1993-02-11

申请号：DE3780307

申请日：1987-04-28

Applicant: IBM

Inventor： ROBBE JEAN-CLAUDE ,  MUNIER JEAN-MARIE ,  PORET MICHEL

IPC: G06F13/42

公开(公告)号：AU604873B2

公开(公告)日：1991-01-03

申请号：AU1462388

申请日：1988-04-14

Applicant: IBM

Inventor： AUSTRUY PIERRE ,  MUNIER JEAN-MARIE ,  PORET MICHAEL

IPC: G06F11/16 ,  G06F11/20 ,  G06F13/10

Abstract: A Control Unit is described, including a Processing Unit (12) controlled by a Service Processor (14), and a plurality of adapters (18) exchanging data and/or control signals with said Processing Unit (PU). For ensuring a continuous operation of the Control Unit, the adapters are partitioned into at least two sets (56,58), and the PU is partitioned into at least two parts (26,28), each set of adapters being connected to a dedicated PU part by a primary bus (52,54). Besides, in order to allow the fallback of a set of adapters onto another PU part if the PU part to which it is normally connected is inoperative, a bus switching device (30) is provided. This bus switching device includes at least two Switch parts (38,40), and each Switch part performs the switching of a given set of adapters onto a given PU part, according to the status of each PU part. Therefore, each Switch part is connected to a given set of adapters by a primary bus (52,54), and to the other sets of adapters by secondary busses (46,48) which become active in fallback mode.

公开(公告)号：DE3853162D1

公开(公告)日：1995-03-30

申请号：DE3853162

申请日：1988-12-23

Applicant: IBM

Inventor： BASSO CLAUDE ,  PAUPORTE ANDRE ,  LEBIZAY GERALD ,  POIRAUD CLEMENT ,  MUNIER JEAN-MARIE

IPC: G06F15/16 ,  G06F9/46 ,  G06F12/06 ,  G06F13/16 ,  G06F15/167 ,  G06F15/177

公开(公告)号：DE3850881T2

公开(公告)日：1995-03-09

申请号：DE3850881

申请日：1988-10-28

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  LIPS JEAN-PIERRE ,  MILLET JEAN-MARC ,  MUNIER JEAN-MARIE ,  NAUDIN BERNARD

IPC: G06F15/16 ,  G06F13/38 ,  G06F13/42 ,  G06F15/167 ,  G06F15/177

Abstract: The memory comprises a linear space and a buffered space, each page of the buffered space is divided in a number m+1 of buffers of equal capacity, with m buffers devoted to the storage of data and one control buffer divided into m control blocks. There is a fixed relationship between one buffer control block and one data buffer. The control blocks are devoted to the storage of buffer and message chaining information. The linear space comprises queue control blocks, with one queue control block per user. The messages are received by memory interface 22 from the source users and then are enqueued in link inbound queues (LIQ) which are dynamically built by taking buffers from the buffered space, chaining the buffers by writing buffer and message chaining information in the corresponding buffer control blocks and writing the queue head and queue tail addresses in the user queue control block. A centralized control means is designed to process enqueue, dequeue and release orders upon requests from a user selected by an arbitrating means. When a link inbound queue becomes not empty, the memory interface 22 sends a dequeue order request to the centralized control means, said request identifying the corresponding user queue control block. The message address is provided in response thereto with the identification of the queue control block of the destination user. Then, the memory interface 22 sends an enqueue request to the centralized control means, said request identifying the address of the message to be enqueued and the queue control block of the destination user. The processing of this enqueue request by the centralized control means causes the messages to be enqueued in an outbound queue from which it is transferred to the destination user, by memory interface 22.

公开(公告)号：CA2120558A1

公开(公告)日：1994-12-31

申请号：CA2120558

申请日：1994-04-05

Applicant: IBM

Inventor： GALAND CLAUDE ,  LEBIZAY GERALD ,  MAUDUIT DANIEL ,  MUNIER JEAN-MARIE ,  PAUPORTE ANDRE ,  SAINT-GEORGES ERIC ,  SPAGNOL VICTOR

IPC: H04L29/06 ,  H04L12/56

Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

公开(公告)号：DE3850881D1

公开(公告)日：1994-09-01

申请号：DE3850881

申请日：1988-10-28

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  LIPS JEAN-PIERRE ,  MILLET JEAN-MARC ,  MUNIER JEAN-MARIE ,  NAUDIN BERNARD

IPC: G06F15/16 ,  G06F13/38 ,  G06F13/42 ,  G06F15/167 ,  G06F15/177

Abstract: The memory comprises a linear space and a buffered space, each page of the buffered space is divided in a number m+1 of buffers of equal capacity, with m buffers devoted to the storage of data and one control buffer divided into m control blocks. There is a fixed relationship between one buffer control block and one data buffer. The control blocks are devoted to the storage of buffer and message chaining information. The linear space comprises queue control blocks, with one queue control block per user. The messages are received by memory interface 22 from the source users and then are enqueued in link inbound queues (LIQ) which are dynamically built by taking buffers from the buffered space, chaining the buffers by writing buffer and message chaining information in the corresponding buffer control blocks and writing the queue head and queue tail addresses in the user queue control block. A centralized control means is designed to process enqueue, dequeue and release orders upon requests from a user selected by an arbitrating means. When a link inbound queue becomes not empty, the memory interface 22 sends a dequeue order request to the centralized control means, said request identifying the corresponding user queue control block. The message address is provided in response thereto with the identification of the queue control block of the destination user. Then, the memory interface 22 sends an enqueue request to the centralized control means, said request identifying the address of the message to be enqueued and the queue control block of the destination user. The processing of this enqueue request by the centralized control means causes the messages to be enqueued in an outbound queue from which it is transferred to the destination user, by memory interface 22.

公开(公告)号：CA1320590C

公开(公告)日：1993-07-20

申请号：CA607308

申请日：1989-08-02

Applicant: IBM

Inventor： CALVIGNAC JEAN ,  LIPS JEAN-PIERRE ,  MILLET JEAN-MARC ,  MUNIER JEAN-MARIE ,  NAUDIN BERNARD

IPC: G06F15/16 ,  G06F13/38 ,  G06F13/42 ,  G06F15/167 ,  G06F15/177

Abstract: MECHANISM FOR TRANSFERRING MESSAGES BETWEEN SOURCE AND DESTINATION USERS THROUGH A SHAPED MEMORY The present invention relates to a mechanism for managing a memory shared between a number of users, so that the users may exchange messages through the memory, in a performant way. The memory comprises a linear space and a buffered space, each page of the buffered space is divided in a number m+1 of buffers of equal capacity, with m buffers devoted to the storage of data and one control buffer divided into m control blocks. There is a fixed relationship between one buffer control block and one data buffer. The control blocks are devoted to the storage of buffer and message chaining information. The linear space comprises queue control blocks, with one queue control block per user. Messages are received by a memory interface from source users and then are enqueued in link inbound queues which are dynamically built by taking buffers from the buffered space, chaining the buffers by writing buffer and message chaining information in the corresponding buffer control blocks and writing the queue head and queue tail addresses in the user queue control block. A centralized control means is designed to process, enqueue, dequeue and release orders upon requests from a user selected by an arbitrating means. When a link inbound queue becomes not empty, the memory interface sends a dequeue order request to the centralized control means, said request identifying the corresponding user FR9-88-009 queue control block. The message address is provided in response thereto with the identification of the queue control block of the destination user. Then, the memory interface sends an enqueue request to the centralized control means, said request identifying the address of the message to be enqueued and the queue control block of the destination user. The processing of this enqueue request by the centralized control means causes the messages to be enqueued in an outbound queue from which it is transferred to the destination user, by the memory interface. FR9-88-009

公开(公告)号：DE3780306T2

公开(公告)日：1993-02-11

申请号：DE3780306

申请日：1987-04-22

Applicant: IBM

Inventor： AUSTRUY PIERRE ,  MUNIER JEAN-MARIE ,  PORET MICHEL

IPC: G06F11/16 ,  G06F11/20

Abstract: A Control Unit is described, including a Processing Unit (12) controlled by a Service Processor (14), and a plurality of adapters (18) exchanging data and/or control signals with said Processing Unit (PU). For ensuring a continuous operation of the Control Unit, the adapters are partitioned into at least two sets (56,58), and the PU is partitioned into at least two parts (26,28), each set of adapters being connected to a dedicated PU part by a primary bus (52,54). Besides, in order to allow the fallback of a set of adapters onto another PU part if the PU part to which it is normally connected is inoperative, a bus switching device (30) is provided. This bus switching device includes at least two Switch parts (38,40), and each Switch part performs the switching of a given set of adapters onto a given PU part, according to the status of each PU part. Therefore, each Switch part is connected to a given set of adapters by a primary bus (52,54), and to the other sets of adapters by secondary busses (46,48) which become active in fallback mode.

公开(公告)号：DE3780307D1

公开(公告)日：1992-08-13

申请号：DE3780307

申请日：1987-04-28

Applicant: IBM

Inventor： ROBBE JEAN-CLAUDE ,  MUNIER JEAN-MARIE ,  PORET MICHEL

IPC: G06F13/42

Abstract: For safe transmission of signals between a control unit (10) and single card or shared field-replaceable-unit adaptors (18), the link includes one dedicated request line (30) per device, an outgoing Device Control Adaptor Data line (34), an outgoing clock line (38) and two incoming lines (32,36) for request acknowledgements ano Device Data signals. The data lines (34,36) connect the shift register (42) of the control unit (10) to that (44) of the selected device (18), forming a loop (74). The second phase of the protocol is started only after error-free completion of the first.