公开(公告)号：JP2000243938A

公开(公告)日：2000-09-08

申请号：JP2000035483

申请日：2000-02-14

Applicant: IBM

Inventor： LAM CHUNG H ,  MILES GLEN L ,  NAKOS JAMES S ,  WILLETS CHRISTA R

IPC: H01L21/8238 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To reduce the size of an NVRAM cell by allowing a cell selection circuit for selecting a cell in an array to respond to a plurality of logic gates and the logic gates to receive data being selected from the array. SOLUTION: A word line 180 is capacitively coupled to floating gates 180f and 228, and at the same time a word line 182 is capacitively coupled to floating gates 182f and 230. Then, four cells indicated by the floating gates 182f and floating gate parts 180f, 228, and 230 are allowed to share each of bit line diffusion regions 224 and 234, and a plurality of logic gates in a selection circuit for selecting the cells receive the data of a selected cell, thus reducing the size of an NVRAM cell for including in a single integrated circuit chip.

公开(公告)号：DE112011102131T5

公开(公告)日：2013-03-28

申请号：DE112011102131

申请日：2011-06-23

Applicant: IBM

Inventor： GAMBINO JEFFREY P ,  MURPHY WILLIAM J ,  PHILIPS BRETT A ,  MOON MATTHEW D ,  NAKOS JAMES S ,  PASTEL PAUL W

IPC: H01L21/02 ,  H01L21/8247 ,  H01L27/115

Abstract: Ferroelektrischer Kondensatormodule, Herstellungsverfahren und Entwurfsstrukturen. Das Herstellungsverfahren eines ferroelektrischen Kondensators beinhaltet das Ausbilden einer Barriereschicht auf einer Isolationsschicht (18) einer CMOS-Struktur (10). Das Verfahren beinhaltet weiterhin das Ausbilden einer oberen Platte (32) und einer untern Platte (28) über der Barriereschicht. Weiterhin beinhaltet das Verfahren das Ausbilden eines ferroelektrischen Materials (30) zwischen der oberen Platte (32) und der unteren Platte (28). Das Verfahren beinhaltet weiterhin die Ummantelung der Barriereschicht, der oberen Platte (32), der unteren Platte (28) und des ferroelektrischen Materials (30) mit einem Ummantelungsmaterial (36). Das Verfahren beinhaltet weiterhin das Ausbilden von Kontakten (20) mit der oberen Platte (32) und der unteren Platte (28) durch das Ummantelungsmaterial (36). Wenigstens der Kontakt (20) mit der oberen Platte (32) und ein Kontakt (20) mit einer Diffusion der CMOS-Struktur stehen durch eine gemeinsame Leitung in elektrischer Verbindung.

公开(公告)号：GB2494362A

公开(公告)日：2013-03-06

申请号：GB201300268

申请日：2011-06-23

Applicant: IBM

Inventor： GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/78

Abstract: Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator (18) layer of a CMOS structure (10). The method further includes forming a top plate (32) and a bottom plate (28) over the barrier layer. The method further includes forming a ferro-electric material (30) between the top plate (32) and the bottom plate (28). The method further includes encapsulating the barrier layer, top plate (32), bottom plate (28) and ferro-electric material (30) with an encapsulating material (36). The method further includes forming contacts (20) to the top plate (32) and bottom plate (28), through the encapsulating material (36). At least the contact (20) to the top plate (32) and a contact (20) to a diffusion of the CMOS structure are in electrical connection through a common wire.

公开(公告)号：GB2494362B

公开(公告)日：2015-05-20

申请号：GB201300268

申请日：2011-06-23

Applicant: IBM

Inventor： GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/78

Abstract: Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator layer of a CMOS structure. The method further includes forming a top plate and a bottom plate over the barrier layer. The method further includes forming a ferro-electric material between the top plate and the bottom plate. The method further includes encapsulating the barrier layer, top plate, bottom plate and ferro-electric material with an encapsulating material. The method further includes forming contacts to the top plate and bottom plate, through the encapsulating material. At least the contact to the top plate and a contact to a diffusion of the CMOS structure are in electrical connection through a common wire.

公开(公告)号：DE112011104378T5

公开(公告)日：2013-09-12

申请号：DE112011104378

申请日：2011-12-07

Applicant: IBM

Inventor： NAKOS JAMES S

IPC: H01L33/36 ,  H01L33/00 ,  H01L33/22

Abstract: Es werden eine Struktur einer lichtemittierenden Diode (LED) (6g) und ein Verfahren zur Herstellung einer lichtemittierenden Diode offenbart. Die Struktur weist Tiefgraben-Metallelektroden (385) auf, zwischen welchen an den Seitenwänden der Elektroden (385) elektrolumineszierendes Material (320) angeordnet ist, welches eine Reihe von lumineszierenden Diodenelementen bildet, die horizontal auf einem Substrat gestapelt sind. (Vgl. 6g.) Das Verfahren zur Herstellung der Struktur der lichtemittierenden Diode kann für eine breite Vielfalt elektrolumineszierender Materialien angewendet werden.

公开(公告)号：MY127563A

公开(公告)日：2006-12-29

申请号：MYPI20020088

申请日：2002-01-11

Applicant: IBM

Inventor： BALLANTINE ARNE W ,  GROVES ROBERT A ,  LUND JENNIFER L ,  NAKOS JAMES S ,  RICE MICHAEL B ,  STAMPER ANTHONY K

IPC: H01L21/768 ,  H01L29/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/822 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/58 ,  H01L27/04 ,  H01M4/58 ,  H01M6/02 ,  H01M6/18 ,  H01M6/42 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/058 ,  H01M10/36 ,  H01M10/42

Abstract: A METHOD AND STURCTURE THAT PROVIDES A BATTERY (420) WITHIN AN INTEGRATED CIRCUIT (400) FOR PROVIDING VOLTAGE TO LOW-CURRENT ELECTRONIC DEVICES (900) THAT EXIST WITHIN THE INTERGRATED CIRCUIT. THE METHOD INCLUDES FRONT-END-OF-LINE (FEOL) PROCESSING FOR GENERATING A LAYER OF ELECTRONIC DEVICES ON A SEMICONDUCTOR WAFER (402), FOLLOWED BY BACK-END-OF-LINE(BEOL) INTEGRATION FOR WIRES THE BEOL INTEGRATION INCLUDES FORMING A MULTILAYERED STRUCTURE OF WIRING LEVELS ON THE LAYER OF ELECTORINC DEVICES. EACH WIRING LEVEL INCLUDES CONDUCTIVE METALLIZATION (E.G., METAL-PLATED VIAS CONDUCTIVE WIRING LINES, ETC) EMBEDDED IN INSULATIVE MATERIAL. THE BATTERY IS FORMED DURING BEOL INTEGRATION WITHIN ONE OR MORE WIRING LEVELS, AND THE CONDUCTIVE METALLIZATION (432,434,442,444)(E.G.,METAL-PALTED VIAS,CONDUCTIVE WIRING LINES, ETC.)EMBEDDED IN INSULATIVE MATERIAL.THE BATTERY IS FORMED DURING BEOL INTEGRATION WITHIN ONE OR MORE WIRING LEVELS,AND THE CONDUCTIVE METALLIZATION CONDUCTIVELY COUPLE POSITIVE (424) AND NEGATIVE (422) TERMINALS OF THE BATERRY TO THE ELECTRONIC DEVICES.THE BATERRY MAY HAVE SEVERAL DIFFERENT TOPOLOGIES RELATIVE TO THE STRUCTURAL AND GEOMETRICAL RELATIONSHIPS AMONG THE BATERRY ELECTRODES AND ELECTROLYTE.MULTIPLE BATTERIES MAY BE FORMED WITHIN ONE OR MORE WIRING LEVELS,AND MAY BE CONDUCTIVELY COUPLE TO THE ELECTRONIC DEVICES.THE MULTIPLE BATERIES MAY BE CONNECTED IN SERIES OR IN PARALLEL.(FIG.1)