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    11.
    发明专利
    未知

    公开(公告)号：DE69920830T2

    公开(公告)日：2005-10-13

    申请号：DE69920830

    申请日：1999-06-19

    Applicant: IBM

    Inventor： CLEMEN RAINER ,  MIELICH HARALD ,  PILLE JUERGEN

    IPC: G11C7/06 ,  G11C11/419 ,  G11C29/12 ,  G11C7/00 ,  G11C29/00

    Abstract: For high-speed single-ended sensing of the signal from a (multi-port) SRAM cell, a configurable half-latch with 2 PFET feedback pathes is proposed, which can be set up either as a bleeder device in the system mode or as keeper devices in the test modes, controlled by a DC signal (TEST). The bleeder and keepers are attached to the bit line and gated by a small ratioed inverter serving as sense amplifier. In case of system mode, a low control signal is applied to the source of the bleeder to limit the bit line up-level to a threshold below the supply voltage Vdd. Thus, discharging the bit line when reading a '0' is fast. Reading a '1' is also fast by skewing the inverter to a PFET/NFET ratio below 1. For chip testing, the control signal is set high to enable the keepers which restore the bit line close to the supply voltage, even when large subthreshold currents try to discharge it via the unselected cells. This turns off the PFET of the inverter, thereby minimizing the DC current. The new approach improves the access time by about 10%, since no speed must be sacrificed for low-power operation during reliability tests at high voltage (1.5x to 2x Vdd) and temperature.

    12.
    发明专利
    未知

    公开(公告)号：DE69920830D1

    公开(公告)日：2004-11-11

    申请号：DE69920830

    申请日：1999-06-19

    Applicant: IBM

    Inventor： CLEMEN RAINER ,  MIELICH HARALD ,  PILLE JUERGEN

    IPC: G11C7/06 ,  G11C11/419 ,  G11C29/12 ,  G11C7/00 ,  G11C29/00

    Abstract: For high-speed single-ended sensing of the signal from a (multi-port) SRAM cell, a configurable half-latch with 2 PFET feedback pathes is proposed, which can be set up either as a bleeder device in the system mode or as keeper devices in the test modes, controlled by a DC signal (TEST). The bleeder and keepers are attached to the bit line and gated by a small ratioed inverter serving as sense amplifier. In case of system mode, a low control signal is applied to the source of the bleeder to limit the bit line up-level to a threshold below the supply voltage Vdd. Thus, discharging the bit line when reading a '0' is fast. Reading a '1' is also fast by skewing the inverter to a PFET/NFET ratio below 1. For chip testing, the control signal is set high to enable the keepers which restore the bit line close to the supply voltage, even when large subthreshold currents try to discharge it via the unselected cells. This turns off the PFET of the inverter, thereby minimizing the DC current. The new approach improves the access time by about 10%, since no speed must be sacrificed for low-power operation during reliability tests at high voltage (1.5x to 2x Vdd) and temperature.

    14.
    发明专利
    未知

    公开(公告)号：DE19632780A1

    公开(公告)日：1998-02-19

    申请号：DE19632780

    申请日：1996-08-15

    Applicant: IBM

    Inventor： BUETTNER STEFAN ,  PILLE JUERGEN ,  WENDEL DIETER ,  WERNICKE FRIEDRICH

    IPC: G11C11/41 ,  G11C11/419 ,  G11C7/00 ,  G11C11/413

    Abstract: A new method is indicated for the restore of bitlines and datalines from memory-cells. All bit- and datalines are switched together during the restore activity so that all restore-FETs can be prepared with the necessary re-charging current. The non-addressed bitlines are then switched off through their bitswitches. In this manner, the dimensions of the re-charging devices can be considerably reduced.

    Current-mode sense amplifier
    15.
    发明专利
    Current-mode sense amplifier 未知

    公开(公告)号：GB2529861A

    公开(公告)日：2016-03-09

    申请号：GB201415668

    申请日：2014-09-04

    Applicant: IBM

    Inventor： FRITSCH ALEXANDER ,  KUGEL MICHAEL ,  PILLE JUERGEN ,  WENDEL DIETER

    IPC: G11C7/06 ,  G11C7/08 ,  G11C8/08 ,  G11C11/419

    Abstract: A current latched sense amplifier CSLA 103 comprising a reference current input terminal (109), a control line input terminal 125, a sense current input terminal 108, an output terminal 106, a first NAND gate 100, a transmission gate 104, and two cross coupled inverters T1, T2, T3, T4 each comprising an nMOSFET device T2, T4. The first NAND gate 100 comprises an output terminal being coupled to the output terminal of the amplifier. The transmission gate 104 comprises two transmission terminals and a gate terminal which is coupled to the control line terminal 125. Sources of the n-MOSFETs are coupled to the sense current input terminal and the reference current input terminal, respectively. One of the transmission terminals is coupled to an input terminal of one of the inverters and the other transmission terminal is coupled to an input terminal of the other inverter. The input terminals of the first NAND gate are coupled to the control line terminal and one of the input terminals of the inverters, respectively. The gate terminal of the transmission gate allows for on/off switching. A first inverter 102 couples one of the input terminals of the first NAND gate to the control line 125. A second NAND gate may be coupled to the second terminal of the amplifier, having a second input controlled by the output of the inverter 102. An electronic circuit may also be included which comprises static memory cells and the current sense amplifier (or current latched sense amplifier). Static Memory Cells may be arranged (figure 4 or 5) such that the data output of each of the cells is coupled via an nMOSFET stack (116 Figure 4) to the sense input of the current sense amplifier.

    20.
    发明专利
    未知

    公开(公告)号：DE10110578A1

    公开(公告)日：2001-10-18

    申请号：DE10110578

    申请日：2001-03-06

    Applicant: IBM

    Inventor： LEENSTRA JENS ,  MUELLER ANTJE ,  PILLE JUERGEN ,  WENDEL DIETER

    IPC: G06F13/18 ,  G06F13/26

    Abstract: A storage device and a method for determining the entry with the highest priority in a buffer memory. The method is characterized by the steps of operating a plurality of priority subfilter circuits each of them covering a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority, and selecting the entry associated with the highest priority subgroup. The storage device is able to be allocated and deallocated repeatedly during processing program instructions in a computer system. The storage device is further characterized by an operator for operating a plurality of priority subfilter circuits. Each of priority subfilter circuits covers a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority. The storage device is still further characterized by a selector for selecting the entry associated with the highest priority subgroup.

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