公开(公告)号：JP2007164171A

公开(公告)日：2007-06-28

申请号：JP2006326354

申请日：2006-12-01

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RANKIN JED H ,  ANDREW J WATTS

IPC: G03F1/08 ,  G03F7/20 ,  H01L21/027

CPC classification number: G03F7/70466 ,  G03F1/70 ,  G03F1/72

Abstract: PROBLEM TO BE SOLVED: To provide a method for patterning a substrate in a way requiring no mask free of defects. SOLUTION: A first mask including a plurality of first features is inspected for defects in the features, and defect data are stored (step 20). A second mask is fabricated as a second sequentially used mask, for patterning a plurality of interconnections between individual regular elements and a plurality of interconnections between the regular elements and redundancy elements (step 50). The regular elements and the redundancy elements are patterned using the first mask (step 60), and the interconnections between the regular elements and the redundancy elements are patterned using the second mask (step 70). As a result, the interconnections are patterned in a way that corrects the detected defects in the first mask. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种不需要没有缺陷的掩模的方法来图案化衬底。 检查包括多个第一特征的第一掩模的特征中的缺陷，并存储缺陷数据（步骤20）。 制造第二掩模作为第二顺序使用的掩模，用于图案化各个规则元件之间的多个互连和常规元件与冗余元件之间的多个互连（步骤50）。 使用第一掩模（步骤60）对普通元件和冗余元件进行图案化，并且使用第二掩模对规则元件和冗余元件之间的互连进行图案化（步骤70）。 结果，以校正第一掩模中检测到的缺陷的方式图案化互连。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007158342A

公开(公告)日：2007-06-21

申请号：JP2006326844

申请日：2006-12-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ABADEER WAGDI W ,  HAUSER MICHAEL J ,  ADKISSON JAMES W ,  RANKIN JED H ,  GAUTHIER ROBERT J JR ,  CHATTY KIRAN V ,  JEFFREY SCOTT BROWN ,  TONTI WILLIAM R

IPC: H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/14 ,  H01L31/12

CPC classification number: H01L23/5256 ,  H01L23/525 ,  H01L27/14609 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of executing an electrical function such as a fusing operation by activation through a chip-embedded photodiode through spectrally selected external light activation, a corresponding structure, and a corresponding circuit. SOLUTION: In conjunction with additional circuit elements to an integrated circuit, incident light with specific intensity/wave length characteristics performs the implementation of repairs. More specifically, failing circuit elements are replaced with redundant ones for yield and/or reliability, and, after a packaged chip is placed in the system, the incident light makes an ESD protection device be disconnected from input pad. No additional pins on the package are necessary. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通过光谱选择的外部光激活，对应的结构和相应的电路来通过芯片嵌入式光电二极管的激活来执行诸如定影操作之类的电功能的方法。

解决方案：结合集成电路的附加电路元件，具有特定强度/波长特性的入射光执行维修。 更具体地，用于产生和/或可靠性的冗余电路元件被替换，并且在将封装芯片放置在系统中之后，入射光使得ESD保护装置与输入焊盘断开连接。 不需要额外的引脚。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2002314094A

公开(公告)日：2002-10-25

申请号：JP2002052160

申请日：2002-02-27

Applicant: IBM

Inventor： BRYANT ANDRES ,  LASKY JEROME B ,  EDWARD J NOWACK ,  RANKIN JED H ,  MIN H TON

IPC: H01L29/43 ,  H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/08 ,  H01L27/11 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for avoiding a floating body effect in an SOI structure. SOLUTION: A semiconductor device includes SOI FETs which include silicon bodies on an insulating layer on a conductive substrate. Gate dielectrics and gates are formed on the surfaces of the silicon bodies, and sources and drains are formed on two sides of the gates. Buried body contacts to substrate conductors are formed under the third side of the gate. The buried body contacts do not extend to the upper face of the silicon bodies. The buried body contacts are separated from the gates by second dielectrics whose thicknesses are generally larger than the thicknesses of the first gate dielectrics. The buried body contacts are plugs made of conductive materials, and the second dielectrics cover the body contacts under the gates. The FETs can be used in a SRAM circuit or any other type of circuit having the silicon on insulator(SOI) structure.

公开(公告)号：AT426246T

公开(公告)日：2009-04-15

申请号：AT01308767

申请日：2001-10-15

Applicant: IBM

Inventor： ADKISSON JAMES W ,  AGNELLO PAUL D ,  BALLANTINE ARNE W ,  DIVAKARUNI RAMA ,  JONES ERIN C ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/336 ,  H01L29/161 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

公开(公告)号：JP2004088101A

公开(公告)日：2004-03-18

申请号：JP2003287197

申请日：2003-08-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ABADEER WAGDI W ,  BROWN JEFFREY S ,  FRIED DAVID M ,  GAUTHIER JR ROBERT J ,  EDWARD J NOWAKU ,  RANKIN JED H ,  TONTI WILLIAM R

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

Abstract: PROBLEM TO BE SOLVED: To provide an improved manufacturing method of an integrated circuit which is made by incorporating both a FinFET and a thick-body device into a single chip. SOLUTION: This manufacturing method of a microelectronic circuit which is made by incorporating both a fin-type field-effect transistor (FinFET) 1801 and a thick-body device 1802 into a single chip can attain an efficiency higher than that of the conventional methods by utilizing common masks and processes. Reduction in the numbers of masks and processes is achieved by utilizing common masks and processes together with several reduction strategies. For example, a structure which usually accompanies a FinFET is formed on a side surface of a thick silicon mesa. A bulk of the silicon mesa is doped to connect to a body contact formed on the opposite side surface of the mesa. This invention also includes the FinFET, thick-body device, and a chip manufactured by the methods associated with the invention. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003204068A

公开(公告)日：2003-07-18

申请号：JP2002361664

申请日：2002-12-13

Applicant: IBM

Inventor： FRIED DAVID M ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide an asymmetrical field effect transistor (FET) having a threshold voltage which is compatible with the present CMOS circuit design and a low-resistance gate electrode. SOLUTION: This asymmetrical FET contains a structure integrated with a p-type gate portion and an n-type gate portion provided on the main body of a vertical semiconductor and the interconnection between the gate portions and a flattened structure on the interconnection. Because of the integrated Fin FET/thick polycilicon-containing gate structure, an Fin FET having the threshold voltage which is compatible with the present CMOS circuit design and the gate electrode the resistivity of which is lower than that of the conventional symmetrical Fin FET can be manufactured. The asymmetrical FET contains the n-type gate portion and p-type gate portion on the main body of the vertical semiconductor and the interconnection between the gate portions and the flattened structure on the interconnection. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2002270697A

公开(公告)日：2002-09-20

申请号：JP2002021072

申请日：2002-01-30

Applicant: IBM

Inventor： BROWN JEFFREY S ,  GAUTHIER ROBERT J JR ,  RANKIN JED H ,  TONTI WILLIAM R

IPC: H01L27/04 ,  H01L21/763 ,  H01L21/768 ,  H01L21/822 ,  H01L27/00 ,  H01L27/02 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide efficient heat radiation which is related to an SOI structure, by forming a semiconductor device located beneath an embedded insulation layer, which is in turn electrically connected to an electrical structure body formed on the SOI structure. SOLUTION: The SOI structure is formed on a bulk semiconductor substrate. A trench, whose one end interfaces with the bulk semiconductor substrate is formed penetrating through the SOI layer. A semiconductor device, comprising a P diffusion region and N diffusion region, is formed on the bulk semiconductor substrate. A conductive plug, which self-matching with the P diffusion region and N diffusion region, while electrically contacting them, is formed in the trench. The semiconductor device formed in the bulk semiconductor substrate can contain an electrostatic discharge(ESD) device. The bulk semiconductor substrate functions as a medium for efficiently radiating heat generated by the (ESD) device, since its thermal conductivity is high.

公开(公告)号：JP2002043581A

公开(公告)日：2002-02-08

申请号：JP2001154502

申请日：2001-05-23

Applicant: IBM

Inventor： JAMES W ADKISSON ,  PAUL D ANGELO ,  BALLANTINE ARNE W ,  CHRISTOPHER S PUTNAM ,  RANKIN JED H

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a dual/wrap-around gate field effect transistor particularly having a short gage length, a low off current and good performance and a method for manufacturing the same. SOLUTION: In the field effect transistor comprising gates each having a length of 10 nm or less and a conductive channel having a width maintained at 1/2 to 1/4 of the length of the gate so that the gates are disposed at least at two sides of the channel, a device having a complete depletion layer is formed without considering the off current. The above-mentioned channel is obtained by forming a groove in a minimum lithographic size, forming sidewalls in the groove and etching a gate structure in a self-alignment manner with the sidewalls. The channel is thereafter epitaxially grown from a source structure in the groove so that the source, the channel and a drain region are integrated in a single crystal structure.

公开(公告)号：WO2011142889A3

公开(公告)日：2012-01-19

申请号：PCT/US2011029498

申请日：2011-03-23

Applicant: IBM ,  RANKIN JED H ,  JAFFE MARK D ,  ANDERSON BRENT A

Inventor： RANKIN JED H ,  JAFFE MARK D ,  ANDERSON BRENT A

IPC: G06F3/042 ,  G06F3/041 ,  G06F3/044

CPC classification number: G06F3/042 ,  G06F3/041 ,  G06F3/0421 ,  G06F3/044 ,  G06F2203/04109

Abstract: Disclosed herein are embodiments of an interface device (100, 200) (e.g., a display, touchpad, touchscreen display, etc.) with integrated power collection functions. In one embodiment, a solar cell (110, 210) or solar cell array can be located within a substrate (10) at a first surface (11) and an array (120, 220) of interface elements can also be located within the substrate (10) at the first surface (11) such that portions of the solar cell(s) (110, 210) laterally surround the individual interface elements (121, 221) or groups thereof. In another embodiment, a solar cell (110, 210) or solar cell array (120, 220) can be located within the substrate (10) at a first surface (11) and an array of interface elements (120, 220) can be located within the substrate (10) at a second surface (12) opposite the first surface (11) (i.e., opposite the solar cell or solar cell array). In yet another embodiment, an array of diodes, which can function as either solar cells (110, 210) or sensing elements, can be within a substrate (10) at a first surface (11) and can be wired to allow for selective operation in either a power collection mode or sensing mode.

Abstract translation: 这里公开了具有集成功率收集功能的接口设备（100,200）（例如，显示器，触摸板，触摸屏显示器等）的实施例。 在一个实施例中，太阳能电池（110,210）或太阳能电池阵列可以位于第一表面（11）处的衬底（10）内，并且界面元件的阵列（120,220）也可以位于衬底 （10）在第一表面（11）处，使得太阳能电池（110,210）的部分横向地围绕各个界面元件（121,221）或其组。 在另一个实施例中，太阳能电池（110,210）或太阳能电池阵列（120,220）可以在第一表面（11）处位于衬底（10）内，并且接口元件阵列（120,220）可以是 位于与第一表面（11）相对的第二表面（12）处（即，与太阳能电池或太阳能电池阵列相对）的衬底（10）内。 在另一个实施例中，可以用作太阳能电池（110,210）或感测元件的二极管阵列可以在第一表面（11）处于衬底（10）内，并且可以被布线以允许选择性操作 在电力收集模式或感测模式下。

公开(公告)号：WO2011059639A3

公开(公告)日：2011-07-28

申请号：PCT/US2010053091

申请日：2010-10-19

Applicant: IBM ,  ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/28247 ,  H01L21/76834 ,  H01L21/76897

Abstract: The present invention relates generally to semiconductor devices and, more specifically, to damascene gates (100; Fig 1C) having protected shorting regions (60) and related methods for their manufacture. A first aspect of the invention provides a method of forming a damascene gate (100) with protected shorting regions (60), the method comprising: forming a damascene gate having: a gate dielectric atop a substrate (12); a gate conductor (40) atop the gate dielectric; a conductive liner laterally adjacent the gate conductor (30); a spacer between the conductive liner and the substrate (20); and a first dielectric atop the gate conductor (60); removing a portion of the conductive liner (30); and depositing a second dielectric (60) atop a remaining portion of the conductive liner (30), such that the second dielectric is laterally adjacent both the first dielectric and the gate.

Abstract translation: 本发明一般涉及半导体器件，并且更具体地涉及具有受保护的短路区域（60）的镶嵌栅极（100;图1C）以及用于其制造的相关方法。 本发明的第一方面提供一种形成具有受保护的短路区域（60）的镶嵌栅极（100）的方法，所述方法包括：形成镶嵌栅极，所述镶嵌栅极具有：衬底（12）顶上的栅极电介质; 在所述栅极电介质顶上的栅极导体（40） 横向邻近栅极导体（30）的导电衬垫; 导电衬垫和衬底（20）之间的间隔件; 以及在所述栅极导体（60）顶上的第一电介质; 去除导电衬里（30）的一部分; 以及在所述导电衬垫（30）的剩余部分顶上沉积第二电介质（60），使得所述第二电介质横向邻近所述第一电介质和所述栅极。