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    12.
    发明专利
    未知

    公开(公告)号：DE3886529T2

    公开(公告)日：1994-06-30

    申请号：DE3886529

    申请日：1988-08-27

    Applicant: IBM

    Inventor： RUDOLPH PETER ,  BOCK DIETRICH W DIPL ING ,  SCHULZE-SCHOELLING HERMANN ING ,  MANNHERZ PETER DIPL ING

    IPC: G01R31/3185 ,  G06F1/24 ,  G06F11/14 ,  G06F1/00 ,  G06F11/00

    Abstract: In computer systems deliberate initializations/resets of the processor latches which represent the internal processor states are necessary to erase only such information which is not required for a subsequent operation (e.g.processing/logging error data) prior to a processor start. One or more reset areas are defined which are initialized /reset in a staggered mode, where in each area a group of latches is assembled which have to be initialized/reset depending on the cause (e.g. power-on) for such a system initialization/reset. The latches within a reset area are connected to form shift registers which are initialized/reset by propagating a binary zero through all latches of the area(s) to be reset.

    QUASI-SYNCHRONOUS INFORMATION TRANSFER AND PHASE ALIGNMENT MEANS FOR ENABLING SAME
    19.
    发明专利
    QUASI-SYNCHRONOUS INFORMATION TRANSFER AND PHASE ALIGNMENT MEANS FOR ENABLING SAME 未知

    公开(公告)号：CA2074008A1

    公开(公告)日：1993-01-21

    申请号：CA2074008

    申请日：1992-07-16

    Applicant: IBM

    Inventor： RUEDINGER JEFFREY J ,  RUDOLPH PETER ,  SHULZE-SCHOELLING HERMANN

    IPC: G06F1/12 ,  G06F12/00 ,  G06F13/42 ,  H04L7/00

    Abstract: GE9-91-010 QUASI-SYNCHRONOUS INFORMATION TRANSFER AND PHASE ALIGNMENT MEANS FOR ENABLING SAME A quasi-synchronous information (clocking, data, control signals) transfer between a master unit A and at least one neighbor unit B offers the advantage that one transfer can occur every cycle where any interface delays are tolerated. When the master unit A sends its internal clock along with data and/or control signals to its neighbor unit B, the last named unit receives this clock and derives any and all locally required clocks from this clock. This keeps unit B exactly at the same frequency as unit A, although a phase shift occurs. Unit B also sends its internal clock along with data and/or control signals to unit A. When the clock signals arrive back at unit A, they will have exactly the same frequency as the internal clock of unit A but also an additional phase shift. Compensation of the overall phase shift will be done by a phase alignment means to which all signals are sent on their way to unit A.

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