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    A.C. POWERED SPEED UP CIRCUIT
    11.
    发明专利
    A.C. POWERED SPEED UP CIRCUIT 未知

    公开(公告)号：CA1111519A

    公开(公告)日：1981-10-27

    申请号：CA277281

    申请日：1977-04-29

    Applicant: IBM

    Inventor： HOWARD DONALD D ,  SCHETTLER HELMUT

    IPC: H03K17/04 ,  H03K17/60 ,  H03K19/013 ,  H03K17/00 ,  H03F3/26

    Abstract: A.C. POWERED SPEED UP CIRCUIT An improved speed up circuit, especially useful with high speed, push pull circuits, is disclosed. This uses only A.C. power to discharge the interelectrode and depletion capacitances of an output transistor thereby eliminating uncontrolled shunt current from the output to ground through the output transistor thereby allowing the output to reach the desired level in a shorter period of time. These desirable results are accomplished by capacitively coupling a resistor-transistor speed up circuit to the base of the output transistor to actively pull the base of the output transistor to ground and discharge the inherent interelectrode and depletion capacitances of the output transistor.

    14.
    发明专利
    未知

    公开(公告)号：DE4221575A1

    公开(公告)日：1994-01-05

    申请号：DE4221575

    申请日：1992-07-01

    Applicant: IBM

    Inventor： KOETZLE GUENTHER ,  KREUTER VOLKER ,  LUDWIG THOMAS ,  SCHETTLER HELMUT

    IPC: G05F3/20 ,  H01L27/02 ,  H01L23/58 ,  H01L27/092 ,  G11C5/14 ,  G06F1/32

    Abstract: An integrated CMOS semiconductor circuit to reduce power consumption in which at least one transistor pair can be operated stably at different supply voltage in that each supply voltage is allocated a threshold voltages which is adjustable via the trough and substrate bias voltages. The substrate of the transistor pair is connected to a substrate bias voltage generator circuit and the trough to a trough bias voltage generator circuit which, dependently upon an input signal representing the height of the supply voltage, sets the height of the bias voltage corresponding to the supply voltage in order to match the threshold voltage to the supply voltage concerned in such a way that the stable operation of the transistor pair is ensured at all times. A data processing system associated to the integrated semiconductor circuit, which, for example, operates at a supply voltage of 3.6 V, a clock frequency of 66 MHz and a relative power consumption of 1, after switching over to a supply voltage of 1.2 V and a clock frequency of below 5 MHz/attains a power consumption of less than 0.01 and an approximately hundredfold increase in the running time for a battery-operated PC.

    DESIGN SYSTEM FOR VLSI CHIPS ARRANGED ON A CARRIER AND MODULE THUS DESIGNED
    15.
    发明专利
    DESIGN SYSTEM FOR VLSI CHIPS ARRANGED ON A CARRIER AND MODULE THUS DESIGNED 未知

    公开(公告)号：CA2024848A1

    公开(公告)日：1991-03-20

    申请号：CA2024848

    申请日：1990-09-07

    Applicant: IBM

    Inventor： SCHETTLER HELMUT ,  SCHULZ UWE ,  ZUEHLKE RAINER

    IPC: H01L21/82 ,  G06F17/50 ,  H01L23/14 ,  H01L23/52 ,  H01L23/538 ,  H01L23/12

    Abstract: DESIGN SYSTEM FOR VLSI CHIPS ARRANGED ON A CARRIER AND MODULE THUS DESIGNED A system design for VLSI chips arranged on a carrier and the module thus designed is described. In a top-down design system synoptically and simultaneously an electrical circuitry is optimized by designing synoptically the chips and the chip carrier. The overall logic is divided in partitions which fit on chips. A chip placement on the carrier is performed considering minimum overall connection length and providing preferably parallel connection. Input/Output contacts are assigned on chips vis-a-vis each other when they correspond. They are connected by parallel lines. The design of the several chips is done from outside to inside, starting with the assigned I/O contacts. Overall, in combining optimum overall design and optimum chip design, a semiconductor thin film silicon multichip module of high yield and performance is provided. A carrier that is included in the design from the beginning, preferably a thin film passive silicon carrier, is used.

    17.
    发明专利
    未知

    公开(公告)号：BR8705233A

    公开(公告)日：1988-05-24

    申请号：BR8705233

    申请日：1987-10-02

    Applicant: IBM

    Inventor： LUDWIG THOMAS ,  SCHETTLER HELMUT ,  WAGNER OTTO ,  ZUHLKE RAINER

    IPC: H03K4/02 ,  H03G11/00 ,  H03K5/02 ,  H03K6/04 ,  H03K17/16 ,  H03K19/0185 ,  G01R31/26

    Abstract: A method for the digital slope control of the output signals of power amplifiers, as well as a power amplifier suitable for carrying out the method as described. One way of representing the actual slope value is via the number of clock pulses applied to a counter during a measuring interval which depends in its duration on the slope. Such a measuring interval is produced by applying the pulses of a ring oscillator containing one of the power amplifiers to another counter until the overflow of the latter. Another mode of representing the actual slope value consists in counting the number of pulses of the ring oscillator during a measuring interval of predetermined duration. Actual and nominal values of the slope are compared. The results of this comparison change the contents of a left/right-shift register. Its parallel outputs influence, via control lines, control inputs of the power amplifiers in order to alter their slope by switching on or off output transistors arranged in parallel with respect to their switching paths.

    Design system for vlsi chips arranged on a carrier and module thus designed
    19.
    发明专利
    Design system for vlsi chips arranged on a carrier and module thus designed 未知

    公开(公告)号：SG46176A1

    公开(公告)日：1998-02-20

    申请号：SG1996000136

    申请日：1989-09-15

    Applicant: IBM

    Inventor： SCHETTLER HELMUT ,  SCHULZ UWE ,  ZUEHLKE RAINER

    IPC: H01L21/82 ,  G06F17/50 ,  H01L23/14 ,  H01L23/52 ,  H01L23/538

    Abstract: A system design for VLSI chips (1,2) arranged on a carrier (3) and the module thus designed is described. In a top-down design system synoptically and simultaneously an electrical circuitry is optimized by designing synoptically the chips and the chip carrier. The overall logic is divided in partitions which fit on chips. A chip placement on the carrier is performed considering minimum overall connection length and providing preferably parallel connection. Input/Output contacts (121 to 221, 131 to 231, 141 to 241) are assigned on chips vis-a-vis each other when they correspond. They are connected by parallel lines. The design of the several chips is done from outside to inside, starting with the assigned I/O contacts. Overall, in combining optimum overall design and optimum chip design, a semiconductor thin film silicon multichip module of high yield and performance is provided. As carrier (3) that is included in the design from the beginning, preferably a thin film passive silicon carrier is used.

    20.
    发明专利
    未知

    公开(公告)号：DE3780482D1

    公开(公告)日：1992-08-27

    申请号：DE3780482

    申请日：1987-01-13

    Applicant: IBM

    Inventor： DANSKY ALLAN H ,  SAVALLE MARTINE MARIE FRANCOIS ,  SCHETTLER HELMUT

    IPC: H03K3/2885 ,  H03K19/013 ,  H03K19/082 ,  H03K19/00 ,  H03K3/288

    Abstract: A "dotted or" logic circuit comprising Current Controlled Gate (CCG) circuits (A,B) is described. In accordance with the present invention, Schottky diodes (D1A,D1B) are cross-coupled between the dotted CCG circuits.Specifically, a Schottky diode (D1A,D1B) of one CCG circuit to the emitter (A2,B2) of the input transistors (T1,T2) of another CCG circuit and vice versa.

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