公开(公告)号：DE3785317D1

公开(公告)日：1993-05-13

申请号：DE3785317

申请日：1987-11-24

Applicant: IBM

Inventor： HWANG WEI ,  SCHUSTER STANLEY EVERETT ,  TERMAN LEWIS MADISON

IPC: G11C11/401 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L21/82

Abstract: A vertical DRAM structure comprising a VMOS transistor and trench capacitor in combination wherein the access transistors are in a V-groove and the capacitors are in two vertical layers. The structure has only a single level of polysilicon and has no contacts. The memory cell circuit is a one-device memory cell, having a single access transistor with its gate (40) connected to a word line (WL), its drain (30) connected to a bit line (BL), and its source (22) connected to a storage capacitor. More particularly, the storage capacitance node (16) is connected to the source (22) of the V-groove access device through a conducting bridge (e.g. 18). An epitaxial layer (26) is grown over a combination of single crystalline material and oxide. Polycrystalline regions in the silicon substrate have an oxide covering. In an alternate version, a single crystal epitaxial layer is disposed over regions consisting of both single crystal and poly crystal Si or polycrystalline material on top of single crystalline material is converted into single crystalline material.

公开(公告)号：DE3774483D1

公开(公告)日：1991-12-19

申请号：DE3774483

申请日：1987-03-06

Applicant: IBM

Inventor： CHAPPELL BARBARA ALANE ,  SCHUSTER STANLEY EVERETT

IPC: H03K19/0185 ,  H03K3/356 ,  H03K19/003 ,  H03K19/0175 ,  G11C8/00

公开(公告)号：DE2225549A1

公开(公告)日：1973-01-11

申请号：DE2225549

申请日：1972-05-26

Applicant: IBM

Inventor： ROCHER EDOUARD YVES ,  SCHUSTER STANLEY EVERETT

IPC: H04L12/46 ,  H04L11/16

Abstract: A method and system is described for handling digital information in the form of addressed messages. The system includes a master communication loop such as a transmission cable. A plurality of sub-loops as well as devices are connected to the master loop through suitable interface units and sub-loop control units. In each of the sub-loops a plurality of devices capable of transmitting and receiving digitally coded messages are connected to the sub-loops through interface units. Two special characters precede the message and permits a sub-loop control unit to take control of the loop to transmit messages and to obtain further messages from the devices in the associated sub-loop. When a unit is permitted to transmit, it produces and transmits a third special character which is received by the other interfaces or stations which are ready to transmit and informs the other interfaces that they may not transmit. After an interface transmits its message or messages, it produces the first and second special characters which is received by the next interface in the loop that is ready to transmit and in this manner, the sequence of transmission is passed around the loop under the control of the interfaces in the loop.

公开(公告)号：MY118598A

公开(公告)日：2004-12-31

申请号：MYPI9804916

申请日：1998-10-28

Applicant: IBM

Inventor： BRONNER GARY BELA ,  EL-KAREH BADIH ,  SCHUSTER STANLEY EVERETT

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108

Abstract: A METHOD OF FORMING INTEGRATED CIRCUIT CHIPS INCLUDING TWO DISSIMILAR TYPE NFETS AND/OR TWO DISSIMILAR TYPE PFETS ON THE SAME CHIP, SUCH AS BOTH THICK AND THIN GATE OXIDE FETS. A DRAM ARRAY MAY BE CONSTRUCTED OF THE THICK OXIDE FETS AND LOGIC CIRCUITS MAY BE CONSTRUCTED OF THE THIN OXIDE FETS ON THE SAME CHIP. FIRST, A GATE STACK (100) INCLUDING A FIRST, THICK GATE SIO21AYER (104) IS FORMED ON A WAFER. THE STACK INCLUDES A DOPED POLYSILICON LAYER (106) ON THE GATE OXIDE LAYER, A SILICIDE LAYER (108) ON THE POLYSILICON LAYER AND A NITRIDE LAYER (110) ON THE SILICIDE LAYER. PART OF THE STACK IS SELECTIVELY REMOVED TO RE-EXPOSE THE WAFER WHERE LOGIC CIRCUITS ARE TO BE FORMED. A THINNER GATE OXIDE LAYER (116) IS FORMED ON THE RE-EXPOSED WAFER. NEXT, GATES ARE FORMED ON THE THINNER GATE OXIDE LAYER AND THIN OXIDE NFETS AND PFETS ARE FORMED AT THE GATES. AFTER SELECTIVELY SILICIDING THIN OXIDE DEVICE REGIONS, GATES ARE ETCHED FROM THE STACK IN THE THICK OXIDE DEVICE REGIONS. FINALLY, SOURCE AND DRAIN REGIONS (140, 142) ARE IMPLANTED AND DIFFUSED FOR THE THICK GATE OXIDE DEVICES.(FIG. 7)

公开(公告)号：GB2328298A

公开(公告)日：1999-02-17

申请号：GB9814444

申请日：1998-07-06

Applicant: IBM

Inventor： MATICK RICHARD EDWARD ,  SCHUSTER STANLEY EVERETT

IPC: G06F12/08

Abstract: A computer memory hierarchy comprises a level one (L1) cache with access/cycle time equal to or faster than a processor cycle time which can deliver at least a logical word or words needed by the processor on each cycle for an L1 HIT and an L2 cache including a directory and data array in which the L2 directory is accessed upon a MISS to the L1 cache. The L2 data array has a mapping from the L2 directory to the data array such that one block needs to be accessed from the data array, the L2 directory performing required address translation and, upon a HIT, starting access to the L2 array for a specific block required for reloading into the L1 cache, and upon a MISS, the L2 cache requesting a block reload from a next level of the hierarchy. The invention allows a DRAM L2 cache to be used in a computer memory hierarchy without compromising overall system performance. To achieve this, the total DRAM access is minimised as much as possible by use of early select techniques and pipelining. The larger DRAM capacity compared to a SRAM gives a substantially better HIT ratio which compensates for any small degradation due to access time.

公开(公告)号：DE68917953T2

公开(公告)日：1995-03-30

申请号：DE68917953

申请日：1989-02-02

Applicant: IBM

Inventor： CHAPPELL BARBARA ALANE ,  CHAPPELL TERRY IVAN ,  SCHUSTER STANLEY EVERETT

IPC: G11C11/413 ,  G11C8/10 ,  G11C11/408 ,  G11C8/00

Abstract: A high performance decoder/driver circuit for a semiconductor memory having A1 to AN (true) and A1 to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A phi PC line is included for receiving a phi PC precharge clock signal thereon and a phi R line is provided for receiving a phi R reset clock signal thereon. The decoder/driver circuit includes an OR decoder means having a plurality of transistor switching devices (1-7) connected to A1 to AN-1 or A1 to AN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on an OR decoder output node (16) depending on the address bits state. The decoder/driver circuit further includes a selection means (8-11) having a plurality of transistor devices including p-channel devices, having diffusion contacts connected to the output node (17, 18) of the decoder and to AN and AN lines to produce a first selection signal when the OR decoder output node is low and the AN line is high and a second selection signal when the OR decoder output node is low and the AN line is high. A driver circuit is connected to the selection means and is responsive to the first selection signal to provide an output signal on a first memory word line (WLi) and is further responsive to the second selection signal to provide an output signal on a second memory word line (WLi+1).

公开(公告)号：DE3685341D1

公开(公告)日：1992-06-25

申请号：DE3685341

申请日：1986-01-09

Applicant: IBM

Inventor： CHAPPELL BARBARA ALANE ,  RAJEEVAKUMAR THEKKEMADATHIL VE ,  SCHUSTER STANLEY EVERETT ,  TERMAN LEWIS MADISON

IPC: H03K19/096 ,  G11C8/10 ,  G11C11/34 ,  G11C11/407 ,  G11C11/413 ,  G11C8/00

Abstract: A decoder/driver circuit for a semiconductor memory having A1 to AN (true) and At to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A Ø PC line is included for receiving a Ø PC precharge clock signal thereon and a Ø R line is provided for receiving a 0 R reset clock signal thereon.The decoder/driver circuit includes a NOR decoder means having a plurality of transistor switching devices 41...44 connected to A1 to AN-1 orA1 toAN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on a decoder output node 1 4 depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices 24, 28 connected to the output node of the decoder to produce a first selection signal when the decoder output node and the AN line is high and a second selection signal when the decoder output node and the AN line is high. A driver circuit is connected to the selection means and is responsive to the output signal of the NOR decoder circuit and the first selection signal to provide an output signal on a first memory word line WLi and is further responsive to the output signal of the NOR decoder circuit and the second selection signal to provide an output sigraal on a second memory word line WLi + 1 .

公开(公告)号：DE3274696D1

公开(公告)日：1987-01-22

申请号：DE3274696

申请日：1982-02-17

Applicant: IBM

Inventor： CHAPPELL BARBARA ALANE ,  SCHUSTER STANLEY EVERETT

IPC: H03K5/02 ,  G11C8/00 ,  G11C8/08 ,  H03K17/04 ,  H03K17/06 ,  H03K17/687

Abstract: An FET high performance driver circuit (20) is especially effective in an environment wherein both large input and output capacitive loads are present. The driver includes a push-pull output circuit (30, 40), a clocked load (25), and a switched transfer depletion FET (27) adapted to decouple the large input capacitive load (62) from an internal node (80) of the driver circuit. This switched decoupling allows an isolation of the large input capacitance from the internal node, whereby the internal node potential can be raised rapidly, and the bootstrapping effectiveness at the internal node can be enhanced so as to significantly increase the circuit operating speed in driving large output capacitative load.

公开(公告)号：DE2961384D1

公开(公告)日：1982-01-28

申请号：DE2961384

申请日：1979-02-01

Applicant: IBM

Inventor： COOK PETER WILLIAM ,  SCHUSTER STANLEY EVERETT

IPC: H01L27/04 ,  G06F1/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H03K5/02 ,  H03K17/082 ,  H03K19/003 ,  H03K19/017 ,  H03K17/08 ,  H02H7/20 ,  H03K19/096 ,  G06F5/00

Abstract: A field effect transistor (FET) protection circuit adapted to operate at high switching speeds and to avoid hot electron operation of voltage stressed FET bootstrap drivers. The circuit comprises a voltage control means adapted to maintain a combined gate and drain to source voltage of FET devices within a characteristic hot electron operational voltage range, by connecting a plurality of FET devices (3, 5) in series, by connecting the common nodes of successive series connected devices (3, 5) to a specified voltage source, by clamping the gate voltage, by providing timing pulses that define particular combinations of gate and drain to source device voltages, or by providing width to length ratios adapted to provide close voltage tracking between input drain voltages and output source voltages. The operation of the hot electron voltage control means is particularly described with respect to embodiments using voltage stressed bootstrap driver FETs to generate on chip clock phases.

公开(公告)号：DE2711829A1

公开(公告)日：1977-10-13

申请号：DE2711829

申请日：1977-03-18

Applicant: IBM

Inventor： COOK PETER WILLIAM ,  PARRISH JAMES THOMAS ,  SCHUSTER STANLEY EVERETT

IPC: H03M1/10 ,  H03K5/08 ,  H03M1/00 ,  H03M1/38 ,  H03K13/05

Abstract: A comparator circuit for comparing two voltage levels in a C-2C A/D and D/A converter, comprising four cross-coupled active devices (FETs) in a latch arrangement whereby an offset voltage is used to compensate for imbalances in the comparator. The comparator includes a first FET having its gate electrode connected to the output of the D/A converter, and a second FET having its gate electrode connected to an analog input voltage. The first and second FETs each have one of their electrodes connected to a common voltage source. A third and a fourth FET have one of their electrodes connected respectively to the other electrode of the first and second FETs at first and second common nodes, respectively. The output of the comparator is provided at one of such first and second common nodes. The first and second nodes are also respectively connected to the gate electrodes of the fourth and third FETs in a cross-coupled arrangement. The other electrode of both the third and fourth FETs are connected to a common phase voltage source. An offset voltage is generated at the input to either of the gate electrodes of the first and second FETs to set the comparator at a balance point and thereby compensate for the differences in the threshold voltages and current carrying capabilities of the four FETs. Also, the comparator has relatively high input impedance, gain and bandwidth.