11.
    发明专利
    未知

    公开(公告)号:IT8021996D0

    公开(公告)日:1980-05-13

    申请号:IT2199680

    申请日:1980-05-13

    Applicant: IBM

    Abstract: 1. Method of making wide, deep recessed isolation trenches in a semiconductor substrate, where a) narrow, shallow trenches (16) are formed in the surface of the semiconductor substrate, said trenches having vertical sidewalls (18) and being separated from each other by profiles with a mesa cross section ; b) the bottom and sidewall surfaces (20, 18) of the trenches (16) formed in the semiconductor substrate, as well as the surfaces of the mesa profile are coated with a masking material (22) ; c) the masking material is removed from the bottom surfaces (20) of the trenches (16) and from the covering surfaces of the profiles by means of reactive ion etching ; d) the semiconductor substrate is exposed to a reactive ion etching, the masking material (24) remaining at the sidewalls of the trenches being used as an etching mask in order to produce a series of deep trenches separated from each other by means of narrow mesa sidewalls (28) ; e) the width of the sidewalls (28) is determined by the layer thickness of the masking material (22) ; and f) the material of the sidewalls is completely thermally oxidized.

    READ HEAD WITH READ TRACK WIDTH DEFINING LAYER THAT PLANARIZES THE WRITE GAP LAYER OF A WRITE HEAD

    公开(公告)号:HU0105162A2

    公开(公告)日:2002-04-29

    申请号:HU0105162

    申请日:1999-11-24

    Applicant: IBM

    Abstract: A read track width defining layer is employed for defining first and second side edges of a read sensor. The read track width defining layer preferably remains in the head to planarize the read head at first and second hard bias and lead layers so as to overcome a problem of write gap curvature in an accompanying write head. The read track width defining layer is defined by a subtractive process about a bilayer photoresist layer. The subtractive process is selective to the read track width defining layer over a read sensor material layer therebelow. Ion milling is then employed for defining first and second side edges of a read sensor layer employing the read track width defining layer as a mask. First and second hard bias and lead layers are then deposited which make contiguous junctions with the first and second side edges of each of the read sensor and read track width defining layers. The photoresist is then removed and the remainder of the read head is completed.

    Read head with read track width defining layer that planarizes the write gap layer of a write head

    公开(公告)号:GB2361801A

    公开(公告)日:2001-10-31

    申请号:GB0115773

    申请日:1999-11-24

    Applicant: IBM

    Abstract: A read track width defining layer (306, 310) is employed for defining first (322) and second side edges of a read sensor. The read track width defining layer (310) preferably remains in the head to planarize the read head at first (330) and second (332) hard bias and lead layers so as to overcome a problem of write gap curvature in an accompanying write head. The read track width defining layer is defined by a subtractive process about a bilayer photoresist layer (308). The subtractive process is selective to the read track width defining layer over a read sensor material layer (304) therebelow. Ion milling is then employed for defining first and second side edges of a read sensor layer employing the read track width defining layer as a mask. First and second hard bias and lead layers are then deposited which make contiguous junctions with the first and second side edges of each of the read sensor and read track width defining layers. The photoresist is then removed and the remainder of the read head is completed.

    19.
    发明专利
    未知

    公开(公告)号:IT1149834B

    公开(公告)日:1986-12-10

    申请号:IT2199680

    申请日:1980-05-13

    Applicant: IBM

    Abstract: 1. Method of making wide, deep recessed isolation trenches in a semiconductor substrate, where a) narrow, shallow trenches (16) are formed in the surface of the semiconductor substrate, said trenches having vertical sidewalls (18) and being separated from each other by profiles with a mesa cross section ; b) the bottom and sidewall surfaces (20, 18) of the trenches (16) formed in the semiconductor substrate, as well as the surfaces of the mesa profile are coated with a masking material (22) ; c) the masking material is removed from the bottom surfaces (20) of the trenches (16) and from the covering surfaces of the profiles by means of reactive ion etching ; d) the semiconductor substrate is exposed to a reactive ion etching, the masking material (24) remaining at the sidewalls of the trenches being used as an etching mask in order to produce a series of deep trenches separated from each other by means of narrow mesa sidewalls (28) ; e) the width of the sidewalls (28) is determined by the layer thickness of the masking material (22) ; and f) the material of the sidewalls is completely thermally oxidized.

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