公开(公告)号：WO2004027824A2

公开(公告)日：2004-04-01

申请号：PCT/US0329085

申请日：2003-09-16

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  SCHUTZ RONALD J ,  ROBL WERNER ,  MALIK RAJEEV ,  CLEVENGER LARRY ,  GLUSCHENKOV OLEG ,  CABRAL CYRIL JR ,  IGGULDEN ROY C ,  WANG YUN-YU ,  WONG KWONG HON ,  MCSTAY IRENE

Inventor： SCHUTZ RONALD J ,  ROBL WERNER ,  MALIK RAJEEV ,  CLEVENGER LARRY ,  GLUSCHENKOV OLEG ,  CABRAL CYRIL JR ,  IGGULDEN ROY C ,  WANG YUN-YU ,  WONG KWONG HON ,  MCSTAY IRENE

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78 ,  H01L

CPC classification number: H01L21/7685 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/76838 ,  H01L21/76855 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4941 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L2221/1078

Abstract: A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.

Abstract translation: 提供了集成电路（12）中的导电结构以及形成该结构的方法，该导电结构包括多晶硅层（30），在多晶硅上包含钛的薄层，在钛 - 氮化镓层上的氮化钨层（34） 在氮化钨层上形成含钨层和钨层。 该结构还包括在多晶硅层和含钛层之间的氮化硅界面区域（38）。 该结构耐受高温处理而在多晶硅层（30）和钨层（32）中基本上不形成金属硅化物，并且在钨层和多晶硅层之间提供低的界面电阻。

公开(公告)号：WO02056342A3

公开(公告)日：2004-01-08

申请号：PCT/US0149138

申请日：2001-12-19

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BOETTCHER STEVEN H ,  HO HERBERT L ,  HOINKIS MARK ,  LEE HYUN KOO ,  WANG YUN-YU ,  WONG KWONG HON

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/76846 ,  H01L21/76858 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer (42) of Ti, followed by a conformal liner layer (46) of CVD TiN, followed in turn by a final liner layer (48) of TA or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the copper to an acceptable amount.

Abstract translation: 在具有铜互连和低k层间电介质的集成电路中，通过使用Ti的第一衬垫层（42），然后使用CVD的保形衬垫层（46），发现并解决了热处理后的开路问题 TiN，然后是TA或TaN的最终衬垫层（48），从而改善通孔和下面的铜层之间的粘附性，同时将由Ti和铜之间的合金化引起的电阻增加减少到可接受的量。

公开(公告)号：WO0203455A3

公开(公告)日：2002-06-13

申请号：PCT/US0120913

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： JAMMY RAJARAO ,  FALTERMEIER CHERYL G ,  SCHROEDER UWE ,  WONG KWONG HON

IPC: C23C16/04 ,  C23C16/34 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8242

CPC classification number: H01L21/76843 ,  C23C16/045 ,  C23C16/34 ,  H01L21/28556 ,  H01L21/76852 ,  H01L21/7687 ,  H01L27/10861 ,  H01L28/82

Abstract: Process for forming highly conformal titanium nitride on a silicon substrate. A gaseous reaction mixture of titanium tetrachloride and ammonia is passed over the semiconductor substrate surface maintained at a temperature of about 350 DEG C to about 800 DEG C. The r atio of titanium tetrachloride to ammonia is about 5:1 to 20:1. The high degree of conformality achieved by the process of the invention allows TiN layers to be deposited on structures with high aspect ratios and on complicated, three-dimensional structures without forming a large seam or void.

Abstract translation: 在硅衬底上形成高保形氮化钛的工艺。 将四氯化钛和氨的气态反应混合物通过保持在约350℃至约800℃温度的半导体衬底表面。四氯化钛与氨的反应混合物为约5：1至20：1。 通过本发明的方法实现的高度的保形性允许TiN层沉积在具有高纵横比的结构上和复杂的三维结构上，而不形成大的接缝或空隙。

公开(公告)号：DE10244570A1

公开(公告)日：2003-04-30

申请号：DE10244570

申请日：2002-09-25

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： IGGULDEN ROY ,  ROBL WERNER ,  SHAFER PADRAIC ,  WONG KWONG HON

IPC: H01L21/768 ,  H01L21/283 ,  H01L23/532

Abstract: The method of filling a damascene structure with liner and tungsten involves coating damascene structure by liner providing poor step coverage, depositing tungsten by chemical vapor deposition, and performing metal isolation process. The resulting damascene structure has improved resistance, resistance spread and favorable adhesion.

公开(公告)号：GB2409932B

公开(公告)日：2006-10-25

申请号：GB0427899

申请日：2004-12-21

Applicant: IBM

Inventor： KU VICTOR ,  STEEGEN AN ,  WANN HSING-JEN ,  WONG KWONG HON

IPC: H01L21/28 ,  H01L21/335 ,  H01L21/04 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: A method is provided for fabricating a gate structure for a semiconductor device in which the gate structure has an inner spacer. A replacement-gate process is used in which material is removed in a gate region to expose a portion of the substrate; a gate dielectric is formed on the exposed portion of the substrate; and an inner spacer layer is formed overlying the gate dielectric and the dielectric material. A silicon layer is then formed which overlies the inner spacer layer. The structure is then planarized so that portions of the silicon layer and inner spacer layer remain in the gate region. A silicide gate structure is then formed from the silicon; the silicide gate structure is separated from dielectric material surrounding the gate by the inner spacer layer. The semiconductor device may include a first gate region and a second gate region with an interface therebetween, with the inner spacer layer covering the interface. When the device has two gate regions, the process may be used in both gate regions, so as to produce separate silicide structures, with an inner spacer separating the two structures.

公开(公告)号：AU2002241651A1

公开(公告)日：2002-07-24

申请号：AU2002241651

申请日：2001-12-19

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： WONG KWONG HON ,  LEE HYUN KOO ,  WANG YUN-YU ,  HO HERBERT L ,  HOINKIS MARK ,  BOETTCHER STEVEN H

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/44 ,  H01L21/4763

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

公开(公告)号：DE10244570B4

公开(公告)日：2007-08-16

申请号：DE10244570

申请日：2002-09-25

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： IGGULDEN ROY ,  ROBL WERNER ,  SHAFER PADRAIC ,  WONG KWONG HON

IPC: H01L21/283 ,  H01L21/768 ,  H01L23/532

Abstract: The method of filling a damascene structure with liner and tungsten involves coating damascene structure by liner providing poor step coverage, depositing tungsten by chemical vapor deposition, and performing metal isolation process. The resulting damascene structure has improved resistance, resistance spread and favorable adhesion.

公开(公告)号：AU2003273328A8

公开(公告)日：2004-04-08

申请号：AU2003273328

申请日：2003-09-16

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CLEVENGER LARRY ,  GLUSCHENKOV OLEG ,  CABRAL CYRIL JR ,  IGGULDEN ROY C ,  WANG YUN-YU ,  WONG KWONG HON ,  MCSTAY IRENE ,  SCHUTZ RONALD J ,  ROBL WERNER ,  MALIK RAJEEV

IPC: H01L20060101 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78

Abstract: A conductive structure in an integrated circuit ( 12 ), and a method of forming the structure, is provided that includes a polysilicon layer ( 30 ), a thin layer containing titanium over the polysilicon, a tungsten nitride layer ( 34 ) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region ( 38 ) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer ( 30 ) and the tungsten layer ( 32 ), and provides low interface resistance between the tungsten layer and the polysilicon layer.

公开(公告)号：DE10330459A1

公开(公告)日：2004-02-26

申请号：DE10330459

申请日：2003-07-05

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DZIOBKOWSKI CHESTER ,  GOEBEL THOMAS ,  HUGHES BRIAN ,  IGGULDEN ROY C ,  IWATAKE MICHAEL M ,  MIURA DONNA D ,  ROBL WERNER ,  SHAFER PADRAIC ,  WONG KWONG HON ,  STRANE JAY W

IPC: H01L21/3205 ,  H01L21/768 ,  H01L21/283

公开(公告)号：DE60141254D1

公开(公告)日：2010-03-25

申请号：DE60141254

申请日：2001-12-19

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： BOETTCHER STEVEN H ,  HO HERBERT L ,  HOINKIS MARK ,  LEE HYUN KOO ,  WANG YUN-YU ,  WONG KWONG HON

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.