公开(公告)号：JP2000138354A

公开(公告)日：2000-05-16

申请号：JP29115799

申请日：1999-10-13

Applicant: IBM

Inventor： RADENS CARL J ,  WEYBRIGHT MARY E

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a memory cell structure, where depletion of majority carrier controlled by the field effect of an embedded strap region that controls access to a trench cell capacitor is used. SOLUTION: A memory cell structure is equipped with a field effect switch provided with a gate terminal 1000 possessed of a trench upper part and a depletion region in a substrate. The range of the depletion region is varied as function of a voltage applied to the gate terminal. Furthermore, a memory device having an isolation collar 400 and a capacitor is provided, and when a field effect switch is at an off-state, a depletion region is superposed on the isolation collar 400, and the depletion region will not be superposed on the isolation collar, when the field effect switch is at an on-state.

公开(公告)号：WO2007027813A3

公开(公告)日：2007-12-06

申请号：PCT/US2006033924

申请日：2006-08-30

Applicant: IBM ,  HSU LOUIS C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  RADENS CARL J ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

Inventor： HSU LOUIS C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  RADENS CARL J ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01P1/10

CPC classification number: H01H50/005 ,  H01H2050/007 ,  Y10T29/4902 ,  Y10T29/49105 ,  Y10T29/49147

Abstract: A MEM switch is described having a free moving element (140) within in micro-cavity (40), and guided by at least one inductive element. The switch consists of an upper inductive coil (170); an optional lower inductive coil (190), each having a metallic core (180,200) preferably made of permalloy; a micro-cavity (40); and a free-moving switching element (140) also made of magnetic material. Switching is achieved by passing a current through the upper coil, inducing a magnetic field in the coil element. The magnetic field attracts the free-moving magnetic element upwards, shorting two open wires (M_I M_r) and thus, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the wires open. When gravity cannot be used, a lower coil becomes necessary to pull the free-moving switching element back and holding it at its original position.

Abstract translation: 描述了一种MEM开关，其具有在微腔（40）内的自由移动元件（140），并由至少一个电感元件引导。 开关由上部感应线圈（170）组成; 可选的下感应线圈（190），每个具有优选由坡莫合金制成的金属芯（180,200） 微腔（40）; 以及也由磁性材料制成的自由移动的开关元件（140）。 通过使电流通过上部线圈来实现切换，从而在线圈元件中产生磁场。 磁场向上吸引自由移动的磁性元件，使两根开放的导线（M_I M_r）短路，从而闭合开关。 当电流停止或反转时，自由移动的磁性元件通过重力返回到微腔的底部并且电线打开。 当不能使用重力时，需要下部线圈将自由移动的开关元件拉回并将其保持在其原始位置。

公开(公告)号：WO0203423A8

公开(公告)日：2002-04-11

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532 ,  H01L

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts because the stacked capacitors are co-planar with the bit lines and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供DRAM单元和制造方法，其通过将堆叠的电容器结构与电触点合并来消除关键的光刻制造步骤。 因为堆叠的电容器与位线共面并且堆叠的电容器位于位线之间提供的绝缘材料中，所以可以使用单个光刻步骤来形成电触点。 与传统的电容器位线（COB）DRAM单元不同，这种位于电容器旁边的位线DRAM单元消除了对电容器专用接触的需要，使得可以用较低的全局地形实现更高的电容。

公开(公告)号：WO02086904A2

公开(公告)日：2002-10-31

申请号：PCT/US0210892

申请日：2002-04-08

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUDELKA STEPHAN P ,  JAIPRAKASH VENKATACHAIAM C ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242 ,  G11C11/00

CPC classification number: H01L27/10864 ,  H01L27/10876 ,  H01L27/10888

Abstract: A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the trench capacitor. The upper portion of the gate conductor is narrower than the lower portion of the gate conductor. The memory cell further includes spacers adjacent the upper portion of the gate conductor and a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor.

Abstract translation: 存储单元的方法具有沟槽电容器和与电容器相邻的垂直晶体管。 垂直晶体管在沟槽电容器上方具有栅极导体。 栅极导体的上部比栅极导体的下部窄。 存储单元还包括邻近栅极导体的上部的间隔物和邻近栅极导体的位线接触。 间隔物减少了位线接触和栅极导体之间​​的短路。 栅极导体上方的栅极接触具有将栅极接触与位线分离的绝缘体。 栅极导体的上部和下部的宽度之间的差异减小了位线接触和栅极导体之间​​的短路。

公开(公告)号：WO0201567A3

公开(公告)日：2002-02-25

申请号：PCT/US0120221

申请日：2001-06-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL J ,  GRUENING ULRIKE

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864 ,  H01L27/10841

公开(公告)号：JP2004128489A

公开(公告)日：2004-04-22

申请号：JP2003310714

申请日：2003-09-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RADENS CARL J ,  RAMACHANDORA DEIVAKARUNI ,  MANDELMAN JACK A

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L29/66181 ,  H01L29/945

Abstract: PROBLEM TO BE SOLVED: To make the interaction between straps smaller than that of the conventional ones. SOLUTION: Each deep trench has its rim in a direction orthogonal to its depth direction. A buried strap 60 extends along the rim. The length of the buried strap 60 is limited to 5-20% of the full length of the rim, and is smaller than one lithography feature size. The buried strap 60, which lies along the rim, is preferably curved and positioned along only one corner of the rim. This structure is useful especially for sub-8F 2 cells. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003037188A

公开(公告)日：2003-02-07

申请号：JP2002142692

申请日：2002-05-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： CLEVENGER LAWRENCE A ,  LOUIS L SHEW ,  RADENS CARL J ,  SHEPARD JR JOSEPH F

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1085 ,  H01L27/10861 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/1203 ,  H01L28/55

Abstract: PROBLEM TO BE SOLVED: To provide a method, as well as structure, for manufacturing a dynamic random access memory device and a related transistor at the same time.
SOLUTION: A channel region and a capacitor opening are formed in a substrate by this method. Then a capacitor conductor is allowed to stick to the capacitor opening. A single insulator layer is formed above the channel region and the capacitor conductor at the same time. The single insulator layer contains a capacitor node dielectrics above the capacitor conductor while a gate dielectrics above the channel region. A single conductor layer is patterned above the single insulator layer at the same time. The single conductor layer contains a gate conductor above the gate dielectrics while a ground plate above the capacitor node dielectrics.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供用于同时制造动态随机存取存储器件和相关晶体管的方法以及结构。 解决方案：通过该方法在衬底中形成沟道区和电容器开口。 然后允许电容器导体粘附到电容器开口。 在通道区域和电容器导体上同时形成单个绝缘体层。 单个绝缘体层在电容器导体上方包含电容器节点电介质，而沟道区域之上的栅极电介质。 单个导体层同时在单个绝缘体层上形成图案。 单导体层包含位于栅极电介质上方的栅极导体，而电容器节点电介质上方的接地板。

公开(公告)号：JP2001044390A

公开(公告)日：2001-02-16

申请号：JP2000209997

申请日：2000-07-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BRONNER GARY ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To obtain non-planar type transistor structure by arranging an active transistor device partially on the sidewall of a deep trench in a cell, and aligning the side wall to a first crystal plane with a crystal orientation along the single- crystal axis. SOLUTION: A deep trench accumulation capacitor 10 is formed in a pad 22 and a substrate 24, and a pattern is formed on the pad 22 using a light lithography step. Then, using such a dry etching step as reactive ion etching, a trench 20 is formed to a desired depth in the substrate 24 through the pad 22. Then, an active transistor device is partially provided on a sidewall 32 of the trench 20, and the sidewall 32 is aligned to first crystal planes (001) and (011) with a crystal orientation set along the single-crystal axis.

公开(公告)号：JP2001044384A

公开(公告)日：2001-02-16

申请号：JP2000220682

申请日：2000-07-21

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： GRUENING ULRIKE ,  RADENS CARL J ,  TOBBEN DIRK

IPC: H01L27/108 ,  H01L21/76 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To reduce a method for forming an embedded plate diffusion region in a deep trench storage capacitor by filling a non-photosensitive underfill material into the lower region of a trench before forming a collar at the upper region of the trench. SOLUTION: A trench 10 is covered with a thin barrier film 30, and a non- photosensitive underfill 16 is filled into the lower region of the trench 10. Then, the barrier film 30 is eliminated by an upper region 223 of the trench 10 by chemical etching using wet solution or the like. Also, the underfill 16 masks a lower region, 24 while the barrier film 30 at the upper region 22 is being removed. Then, the underfill 16 is removed from a lower region by stripping or the like by a chemical containing HF, and a collar 32 is formed at the upper region 22 by thermal oxidation growth or the like by the local oxidation process.

公开(公告)号：WO2006055357A2

公开(公告)日：2006-05-26

申请号：PCT/US2005040524

申请日：2005-11-09

Applicant: IBM ,  CHENG KANGGUO ,  RADENS CARL J

Inventor： CHENG KANGGUO ,  RADENS CARL J

IPC: H01L21/20

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1087 ,  H01L27/10894 ,  H01L27/1203 ,  H01L27/1207

Abstract: Methods of forming a deep trench capacitor memory device and logic devices on a single chip with hybrid surface orientation. The methods allow for fabrication of a system-on-chip (SoC) with enhanced performance including n-type complementary metal oxide semiconductor (CMOS) device SOI arrays and logic transistors on (100) surface orientation silicon, and p-type CMOS logic transistors on (110) surface orientation silicon. In addition, the method fabricates a silicon substrate trench capacitor within a hybrid surface orientation SOI and bulk substrate. Cost-savings is realized in that the array mask open and patterning for silicon epitaxial growth is accomplished in the same step and with the same mask.

Abstract translation: 在具有混合表面取向的单个芯片上形成深沟槽电容器存储器件和逻辑器件的方法。 该方法允许制造具有增强性能的片上系统（SoC），包括在（100）表面取向硅上的n型互补金属氧化物半导体（CMOS）器件SOI阵列和逻辑晶体管以及p型CMOS逻辑晶体管 on（110）表面取向硅。 此外，该方法在混合表面取向SOI和体基板内制造硅衬底沟槽电容器。 实现节省成本，其中阵列掩模开放和用于硅外延生长的图案化在相同的步骤和相同的掩模中完成。