Abstract:
A method and semiconductor device. In the method, at least one partial via (26) is etched in a stacked structure and a border (32) is formed about the at least one partial via (26). The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer (22).
Abstract:
PROBLEM TO BE SOLVED: To provide a shielded interconnection for reducing capacitive coupling between interconnecting lines in an integrated circuit device having interconnecting lines isolated by an interlayer dielectric. SOLUTION: Interconnecting lines are provided with a thin side wall conductive shield isolated from interconnecting lines by a thin side wall dielectric. Crosstalk between adjacent lines in an interconnection layer is reduced by a side wall shield. The thin side wall dielectric material can be selected to reduce capacitance between the side wall shield and the interconnecting lines. An interlayer dielectric can be selected to enhance defect resistance and mechanical strength during fabrication of a device. A method for fabricating shielded interconnections is also provided.
Abstract:
PROBLEM TO BE SOLVED: To provide means for making an ultra-low k dielectric material which is compatible with a C4/wire bond structure. SOLUTION: The manufacturing method and structure of a semiconductor chip comprises a plurality of interconnecting metallization layers, at least one deformable dielectric material layer covering the interconnecting metallization layers, at least one I/O bonding pad, and a support structure including a fairly rigid dielectric in supporting relation with the pads and avoiding crushing of the deformable dielectric material layer.
Abstract:
A chip includes a CMOS structure having a bulk device (20) disposed in a first region (24) of a semiconductor substrate (50) in conductive communication with an underlying bulk region (18) of the substrate, the first region (24) and the bulk region (20) having a first crystal orientation. A SOI device (10) is disposed in a semiconductor-on-insulator ("SOI") layer (14) separated from the bulk region of the substrate by a buried dielectric layer (16), the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor (11) in conductive communication with a gate conductor (21) of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.
Abstract:
Dummy Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a bumper extending from a Micro-Electro-Mechanical System (MEMS) beam structure provided within a cavity structure. The method further includes forming a dummy landing structure on an opposing side of the cavity structure from the MEMS beam, which is laterally offset from the bumper when the MEMS beam is in a non-actuated state.
Abstract:
PROBLEM TO BE SOLVED: To provide a new dual damascene wiring structure that improves the efficiency of dual damascene wiring by improving a dual damascene wiring formation method. SOLUTION: This method concerns the formation of a dual damascene interconnection structure and a related structure. In this formation, the related structure includes a dual damascene wiring in a dielectric substance layer. The above dual damascene wiring is extended into the dielectric substance layer at a distance shorter than the thickness of the corresponding dielectric substance layer, and a dual damascene via bar is integrated with the bottom of the dual damascene wiring and is extended toward the bottom of the dielectric substance later from that bottom. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor device of high strength that lowers an effective dielectric constant k eff , maintains an inter-level vertical capacity in an interconnection at a low level and a manufacturing method of the same. SOLUTION: The method of manufacturing the device comprises a step for providing a structure having an insulating layer 120 of at least one interconnection 130 and a step for forming a sublithographic template mask 150 on the insulating layer. A sublithographic feature 135a is formed in the vicinity of at least one intereconnection by performing etching on the insulating layer through the sublithographic template mask using a selective etching step. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a more reliable damascene capacitor structure by preventing the occurrence of leakage and dielectric breakdown between capacitor plates. SOLUTION: A capacitor device is provided with a trench which is formed into an inter-level dielectric insulator layer and has sidewalls, a first thin lower conductor plate 32 formed on the bottom of the trench, and a second upper conductor plate 44 having a surface which is commonly formed as the surface of the dielectric insulator layer also. The capacitor device is also provided with a dielectric layer 42 formed between the conductor plates 32 and 44. The dielectric layer 42 prevents one of the conductor plates 32 and 44 from extending to the sidewalls of the trench and at least one upper corner of the conductor plate from extending toward the upper part of the trench.