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    SHIELDED INTERCONNECTION FOR INTEGRATED CIRCUIT DEVICE
    14.
    发明专利
    SHIELDED INTERCONNECTION FOR INTEGRATED CIRCUIT DEVICE 失效

    公开(公告)号：JP2001308184A

    公开(公告)日：2001-11-02

    申请号：JP2001070270

    申请日：2001-03-13

    Applicant: IBM

    Inventor： JONATHAN D CHAPPURUSOKORU ,  IVERS THOMAS H ,  MCGAHAY VINCENT J ,  STAMPER ANTHONY K

    IPC: H01L23/522 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

    Abstract: PROBLEM TO BE SOLVED: To provide a shielded interconnection for reducing capacitive coupling between interconnecting lines in an integrated circuit device having interconnecting lines isolated by an interlayer dielectric. SOLUTION: Interconnecting lines are provided with a thin side wall conductive shield isolated from interconnecting lines by a thin side wall dielectric. Crosstalk between adjacent lines in an interconnection layer is reduced by a side wall shield. The thin side wall dielectric material can be selected to reduce capacitance between the side wall shield and the interconnecting lines. An interlayer dielectric can be selected to enhance defect resistance and mechanical strength during fabrication of a device. A method for fabricating shielded interconnections is also provided.

    PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS
    16.
    发明申请
    PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS 审中-公开
    在混合方向晶体管中对充电损害的保护

    公开(公告)号：WO2007115146B1

    公开(公告)日：2008-06-05

    申请号：PCT/US2007065604

    申请日：2007-03-30

    Applicant: IBM ,  HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

    Inventor： HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

    IPC: H02H9/00

    CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

    Abstract: A chip includes a CMOS structure having a bulk device (20) disposed in a first region (24) of a semiconductor substrate (50) in conductive communication with an underlying bulk region (18) of the substrate, the first region (24) and the bulk region (20) having a first crystal orientation. A SOI device (10) is disposed in a semiconductor-on-insulator ("SOI") layer (14) separated from the bulk region of the substrate by a buried dielectric layer (16), the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor (11) in conductive communication with a gate conductor (21) of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

    Abstract translation: 芯片包括CMOS结构，其具有设置在半导体衬底（50）的第一区域（24）中的本体器件（20），该半导体衬底（50）与衬底的下面的体区域（18）导通连通，第一区域（24）和 本体区域（20）具有第一晶体取向。 SOI器件（10）通过埋入介质层（16）设置在与衬底的本体区域分离的绝缘体上半导体（“SOI”）层14中，SOI层具有不同的晶体取向 第一个晶体取向。 在一个示例中，体器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，体器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与本体器件的栅极导体（21）导电连通的栅极导体（11）时，SOI器件可能会发生充电损坏，除了存在与体积反向偏置导电连通的二极管 地区。 当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导到体区。

    MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) STRUCTURES AND DESIGN STRUCTURES
    17.
    发明申请
    MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) STRUCTURES AND DESIGN STRUCTURES 审中-公开
    微电子机械系统（MEMS）结构和设计结构

    公开(公告)号：WO2014181202A2

    公开(公告)日：2014-11-13

    申请号：PCT/IB2014060145

    申请日：2014-03-25

    Applicant: IBM ,  IBM CHINA LTD

    Inventor： STAMPER ANTHONY K

    CPC classification number: B81B3/001

    Abstract: Dummy Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a bumper extending from a Micro-Electro-Mechanical System (MEMS) beam structure provided within a cavity structure. The method further includes forming a dummy landing structure on an opposing side of the cavity structure from the MEMS beam, which is laterally offset from the bumper when the MEMS beam is in a non-actuated state.

    Abstract translation: 公开了虚拟微机电系统（MEMS）结构，制造方法和设计结构。 该方法包括形成从设置在空腔结构内的微电子机械系统（MEMS）梁结构延伸的保险杠。 该方法还包括在空腔结构的与MEMS光束相对的一侧上形成虚拟着陆结构，当MEMS射束处于非致动状态时，其从该保险杠侧向偏移。

    Dual damascene wiring and its forming method
    18.
    发明专利
    Dual damascene wiring and its forming method 有权
    双面接线及其成型方法

    公开(公告)号：JP2006054433A

    公开(公告)日：2006-02-23

    申请号：JP2005183686

    申请日：2005-06-23

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： MCDEVITT THOMAS L ,  STAMPER ANTHONY K

    IPC: H01L21/768 ,  H01L21/822 ,  H01L27/04

    CPC classification number: H01L21/76838 ,  H01L21/76802 ,  H01L21/76808 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a new dual damascene wiring structure that improves the efficiency of dual damascene wiring by improving a dual damascene wiring formation method. SOLUTION: This method concerns the formation of a dual damascene interconnection structure and a related structure. In this formation, the related structure includes a dual damascene wiring in a dielectric substance layer. The above dual damascene wiring is extended into the dielectric substance layer at a distance shorter than the thickness of the corresponding dielectric substance layer, and a dual damascene via bar is integrated with the bottom of the dual damascene wiring and is extended toward the bottom of the dielectric substance later from that bottom. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种新的双镶嵌布线结构，通过改进双镶嵌布线形成方法来提高双镶嵌布线的效率。

    解决方案：该方法涉及形成双镶嵌互连结构和相关结构。 在该结构中，相关结构包括电介质层中的双镶嵌布线。 上述双镶嵌布线以比对应的电介质层的厚度短的距离延伸到电介质层中，并且双镶嵌通孔条与双镶嵌布线的底部一体化并且朝向底部延伸 电介质物质晚于该底部。 版权所有（C）2006，JPO＆NCIPI

    CAPACITOR DEVICE AND METHOD OF FORMING CAPACITOR
    20.
    发明专利
    CAPACITOR DEVICE AND METHOD OF FORMING CAPACITOR 审中-公开

    公开(公告)号：JP2002313939A

    公开(公告)日：2002-10-25

    申请号：JP2002060480

    申请日：2002-03-06

    Applicant: IBM

    Inventor： STAMPER ANTHONY K

    IPC: H01L27/04 ,  H01L21/02 ,  H01L21/334 ,  H01L21/768 ,  H01L21/822 ,  H01L27/08

    Abstract: PROBLEM TO BE SOLVED: To provide a more reliable damascene capacitor structure by preventing the occurrence of leakage and dielectric breakdown between capacitor plates. SOLUTION: A capacitor device is provided with a trench which is formed into an inter-level dielectric insulator layer and has sidewalls, a first thin lower conductor plate 32 formed on the bottom of the trench, and a second upper conductor plate 44 having a surface which is commonly formed as the surface of the dielectric insulator layer also. The capacitor device is also provided with a dielectric layer 42 formed between the conductor plates 32 and 44. The dielectric layer 42 prevents one of the conductor plates 32 and 44 from extending to the sidewalls of the trench and at least one upper corner of the conductor plate from extending toward the upper part of the trench.

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