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    Chain Ferroelectric Random Access Memory arrangement has selection transistors in the form of depletion type field effect transistors to prevent leakage currents in the rest state
    17.
    发明专利
    Chain Ferroelectric Random Access Memory arrangement has selection transistors in the form of depletion type field effect transistors to prevent leakage currents in the rest state 未知

    公开(公告)号：DE10042222A1

    公开(公告)日：2002-03-14

    申请号：DE10042222

    申请日：2000-08-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROEHR THOMAS ,  BOEHM THOMAS ,  HOENIGSCHMID HEINZ

    IPC: G11C11/22

    Abstract: The CFRAM arrangement has a number of memory cells each consisting of a ferroelectric storage capacitor and a selection transistor. Each block of selection transistors is associated with a block-select-transistor. The selection transistors and the block-select-transistor are arranged between a plate line and a bit line and the selection transistors are each connected to word lines. The selection transistors are depletion type FETs. The CFRAM arrangement has a number of memory cells (Z0-Z3) each consisting of a ferroelectric storage capacitor (Cferro0...) and a selection transistor (Tdep10..). Each block of selection transistors is associated with a block-select-transistor (TEnh). The selection transistors and the block-select-transistor are arranged between a plate line (PL) and a bit line (BL) and the selection transistors are each connected to word lines (WL0...). The selection transistors are depletion type field effect transistors.

    Digital circuit e.g. for FeRAM
    19.
    发明专利
    Digital circuit e.g. for FeRAM 未知

    公开(公告)号：DE10011180A1

    公开(公告)日：2001-09-27

    申请号：DE10011180

    申请日：2000-03-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  MANYOKI ZOLTAN ,  LAMMERS STEFAN ,  KANDOLF HELMUT

    IPC: G11C29/04 ,  G11C29/24 ,  G11C29/46 ,  G11C29/00

    Abstract: The circuit includes an information memory with an addressing device with a decoder and an input circuit. The number of address terminal contacts (11,12) is equal to a sum Z+S, where Z is the number of bits required by M elements, and S is the number of bits required by N elements. The numbers P and Q are selected so that for addressing P elements K less than or equal to (Z-2) bits are required and for addressing Q elements L less than or equal to (S-2) bits are required. The input circuit (11-36) has an additional control bit contact (13) and a switchover device (31-34) which receives a control bit to set a first operating mode or a second, third or fourth operating mode accordingly.

    20.
    发明专利
    未知

    公开(公告)号：DE50015406D1

    公开(公告)日：2008-11-27

    申请号：DE50015406

    申请日：2000-12-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BOEHM THOMAS ,  BRAUN GEORG ,  HOENIGSCHMID HEINZ ,  ROEHR THOMAS DR

    IPC: G11C11/406 ,  G11C14/00 ,  G11C11/22

    Abstract: The memory arrangement has a memory cell field (7) with a number of memory cells driven via word lines and bit lines and a refresh logic circuit (8) for refreshing the memory contents of the memory cell field. A comparator circuit (9) compares a characteristic parameter of at least one memory cell (10) with a reference value (VREF) and activates the refresh logic as required.

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