公开(公告)号：DE102004040505A1

公开(公告)日：2006-03-02

申请号：DE102004040505

申请日：2004-08-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HALIK MARCUS ,  DEHM CHRISTINE ,  KLAUK HAGEN ,  ZSCHIESCHANG UTE ,  SCHMID GUENTER

IPC: H01L21/76 ,  H01L51/30

Abstract: The invention relates to a semiconductor circuit arrangement (10) and to a method for the production thereof, in which a protective material region (50) made of poly(para-xylene) is formed for the material separation of a first circuit region (30) and a second circuit region (40).

公开(公告)号：DE10057806A1

公开(公告)日：2002-06-06

申请号：DE10057806

申请日：2000-11-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  HOENIGSCHMID HEINZ ,  DEHM CHRISTINE

IPC: H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L21/8239 ,  H01L27/105

Abstract: The contact plugs (26) to the top capacitor electrodes of each memory cell are not manufactured from below but from above. First the capacitor formed by the upper (22) and lower (24,24s) capacitor electrodes and the dielectric (23) are manufactured. A hole for the contact plug to the top electrode is then etched through the top electrode and the dielectric and filled with a conductive material to connect top electrode with the substrate.

公开(公告)号：DE69838502D1

公开(公告)日：2007-11-15

申请号：DE69838502

申请日：1998-06-26

Applicant: INFINEON TECHNOLOGIES AG ,  ADVANCED TECH MATERIALS

Inventor： HINTERMAIER FRANK S ,  DEHM CHRISTINE ,  HOENLEIN WOLFGANG ,  VAN BUSKIRK PETER C ,  ROEDER JEFFREY F ,  HENDRIX BRYAN C ,  BAUM THOMAS H ,  DESROCHERS DEBRA A

IPC: B32B9/00 ,  C23C16/00 ,  C01G35/00 ,  C23C16/40 ,  C23C16/56 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8246 ,  H01L27/105

Abstract: A low temperature CVD process using a tris (beta-diketonate) bismuth precursor for deposition of bismuth ceramic thin films suitable for integration to fabricate ferroelectric memory devices. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.

公开(公告)号：DE102004025676A1

公开(公告)日：2005-12-22

申请号：DE102004025676

申请日：2004-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLAUK HAGEN ,  HALIK MARCUS ,  ZSCHIESCHANG UTE ,  SCHMID GUENTER ,  DEHM CHRISTINE

IPC: G11C13/00 ,  G11C13/02 ,  H01L27/105 ,  H01L27/108 ,  H01L27/28 ,  H01L51/20 ,  G11C11/46 ,  H01L27/10

公开(公告)号：DE10212878A1

公开(公告)日：2003-10-16

申请号：DE10212878

申请日：2002-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHMID GUENTER ,  HALIK MARCUS ,  KLAUK HAGEN ,  DEHM CHRISTINE ,  HANEDER THOMAS ,  MIKOLAJICK THOMAS

IPC: G11C13/02 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/28 ,  H01L51/20 ,  H01L51/10

Abstract: Semiconductor circuit arrangement comprises a pair of complementary field effect transistor devices (T1, T2) each having a gate region, first and second source/drain regions (SD11, SD12, SD21, SD22), and a channel region provided between each source/drain region. The gate regions and especially their gate electrodes are electrically coupled together via a capacitor arrangement (C1, C2). Preferably organic semiconductor material is provided in each channel region in the field effect transistor devices. The organic semiconductor material is a p-conducting or n-conducting semiconductor material. The gate electrode arrangement of the gate regions is electrically insulated by insulating regions (I1, I2) from the source/drain regions and the channel regions.

公开(公告)号：DE10053172A1

公开(公告)日：2002-05-16

申请号：DE10053172

申请日：2000-10-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SITARAM ARKALGUD ,  MAZURE CARLOS ,  DEHM CHRISTINE

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L23/522 ,  H01L21/8239 ,  H01L27/105

公开(公告)号：DE10053171A1

公开(公告)日：2002-05-16

申请号：DE10053171

申请日：2000-10-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SITARAM ARKALGUD ,  DEHM CHRISTINE

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8239

Abstract: Production of a ferroelectric or paraelectric layer containing a metal oxide comprises preparing a substrate (32); applying a metal oxide-containing layer (33) on the substrate; implanting oxygen in a metal oxide-containing layer or in an auxiliary layer; and heat treating. An Independent claim is also included for the production of a DRAM storage cell comprising forming a switching transistor on a substrate; applying a first insulating layer (4); and applying a storage capacitor produced from the ferroelectric or paraelectric layer. Preferred Features: The heat treatment is carried out in an inert atmosphere. The substrate is made from platinum, palladium, iridium, rhodium, ruthenium, or osmium, a conductive oxide of these or another conductive oxide.

公开(公告)号：DE69838502T2

公开(公告)日：2008-07-24

申请号：DE69838502

申请日：1998-06-26

Applicant: INFINEON TECHNOLOGIES AG ,  ADVANCED TECH MATERIALS

Inventor： HINTERMAIER FRANK S ,  DEHM CHRISTINE ,  HOENLEIN WOLFGANG ,  VAN BUSKIRK PETER C ,  ROEDER JEFFREY F ,  HENDRIX BRYAN C ,  BAUM THOMAS H ,  DESROCHERS DEBRA A

IPC: B32B9/00 ,  C23C16/00 ,  C01G35/00 ,  C23C16/40 ,  C23C16/56 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8246 ,  H01L27/105

Abstract: A low temperature CVD process using a tris (beta-diketonate) bismuth precursor for deposition of bismuth ceramic thin films suitable for integration to fabricate ferroelectric memory devices. Films of amorphous SBT can be formed by CVD and then ferroannealed to produce films with Aurivillius phase composition having superior ferroelectric properties suitable for manufacturing high density FRAMs.

公开(公告)号：DE50015110D1

公开(公告)日：2008-05-29

申请号：DE50015110

申请日：2000-06-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER ,  DEHM CHRISTINE

IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/02 ,  H01L21/8246 ,  H01L27/105

Abstract: The invention provides a semiconductor memory component with random access, also having a structure which is differentiated into memory cells and logic regions and has a lower oxide layer arranged on a silicon substrate and an upper oxide layer arranged on the lower oxide layer, each memory cell comprising at least one transistor in the transition region between silicon substrate and lower oxide layer and a capacitor in the transition region between lower oxide layer and upper oxide layer, which capacitor is connected to the transistor via a contact hole, which is filled with metal, in the lower oxide layer and comprises a ferroelectric arranged between two electrodes, the electrode which is connected to the transistor and adjoins the lower oxide layer having a relatively great thickness, and each logic region comprising at least one transistor in the transition region between silicon substrate and lower oxide layer, which transistor is connected to an electrode on the topside of the upper oxide layer via a contact hole, which is filled with metal, in the lower oxide layer and the upper oxide layer. According to the invention, it is provided that between the capacitors of the memory cells and the contact holes in the logic regions, level compensation between the topology of the memory cells and of the logic regions is created by dummy structures.

公开(公告)号：DE102004025675A1

公开(公告)日：2005-12-22

申请号：DE102004025675

申请日：2004-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLAUK HAGEN ,  HALIK MARCUS ,  ZSCHIESCHANG UTE ,  SCHMID GUENTER ,  DEHM CHRISTINE

IPC: G11C13/02 ,  H01L27/28 ,  H01L51/00 ,  H01L51/05 ,  H01L51/20 ,  H01L27/10 ,  G11C13/00

Abstract: An integrated semiconductor memory with a cell array is disclosed. In one embodiment the memory includes a multiplicity of memory cells arranged in rows and columns. In at least one memory cell, an organic selection transistor is integrated in a stack arrangement above an organic storage element.