公开(公告)号：DE10301480B4

公开(公告)日：2006-04-20

申请号：DE10301480

申请日：2003-01-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STOCKEN CHRISTIAN ,  DOBLER MANFRED ,  EGGERS GEORG

IPC: H01L23/50 ,  H01L21/50 ,  H01L21/60 ,  H01L23/495 ,  H05K3/34

Abstract: The method involves one or more stamping process steps in which at least one pin is stamped out of a base body, especially a lead frame. The pin or a section of the pin is coated with a separate metal coating only after final stamping out of the pin. The end face of the outer end section of the pin is also coated with the metal coating. Independent claims are also included for the following: (a) a housing, especially for semiconducting components (b) and a semiconducting component pin.

公开(公告)号：DE10011179B4

公开(公告)日：2005-06-30

申请号：DE10011179

申请日：2000-03-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BEER PETER ,  DOBLER MANFRED ,  KRAUSE GUNNAR

IPC: G01K7/01 ,  G01R31/30 ,  H01L23/62 ,  H01L21/66

公开(公告)号：DE10335618A1

公开(公告)日：2005-03-10

申请号：DE10335618

申请日：2003-08-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DOBLER MANFRED ,  BENZINGER HERBERT ,  KLIEWER JOERG ,  PROELL MANFRED

IPC: G11C8/08 ,  G11C11/406 ,  G11C11/408 ,  G11C11/407

Abstract: A semiconductor memory includes storage cells ( 2 ) that have storage capacitors and transistors with an electrode, which is electrically biasable with two different electrical potentials (V 1, V 2 ) in order to open and close the transistor. The electrode potential (V 2 ) intended for the off state of the transistor is a temperature-dependent potential, the value of which is controlled temperature-dependently by the semiconductor memory ( 1 ) so that the second electrical potential (V 2 ) becomes more different from the first electrical potential (V 1 ) as the temperature (T) increases.

公开(公告)号：DE10315087B3

公开(公告)日：2004-05-13

申请号：DE10315087

申请日：2003-04-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DOBLER MANFRED

IPC: G11C11/406 ,  G11C7/06

Abstract: The memory cell refreshing method has the word line (WL) coupled to the memory cell (2) activated, with amplification of the charge potential of the bit lines (BL) of the bit line pair (BLP) in the direction of a higher or a lower refresh potential, in dependence on the charge information held in the memory cell, before de-activation of the word line and charging of the bit lines to a refresh mean potential. The potential difference between the higher refresh potential and the mean refresh potential is greater than the potential difference between the higher charge potential and the mean potential during the read-out of the memory cell. An Independent claim for a memory circuit is also included.

公开(公告)号：DE10220354B4

公开(公告)日：2004-03-11

申请号：DE10220354

申请日：2002-05-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DOBLER MANFRED

IPC: G11C5/14 ,  G11C11/4074 ,  G06F11/267

Abstract: A memory circuit includes one or several voltage generators for generating operating voltages for memory elements of the memory circuit and a means for selectively setting a current which may be supplied by one of the one or several voltage generators depending on an operating frequency for the memory circuit.

公开(公告)号：DE10220354A1

公开(公告)日：2003-12-04

申请号：DE10220354

申请日：2002-05-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DOBLER MANFRED

IPC: G11C5/14 ,  G11C11/4074 ,  G06F11/267

Abstract: A memory circuit includes one or several voltage generators for generating operating voltages for memory elements of the memory circuit and a means for selectively setting a current which may be supplied by one of the one or several voltage generators depending on an operating frequency for the memory circuit.

公开(公告)号：DE10143764A1

公开(公告)日：2003-03-27

申请号：DE10143764

申请日：2001-09-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STOCKEN CHRISTIAN ,  CORDES ERIC ,  EGGERS GEORG ,  DOBLER MANFRED

IPC: H01L21/60 ,  H01L21/607 ,  H01L23/13 ,  H05K3/34 ,  H01L21/58

Abstract: During attachment, the temperature of memory components (especially micro-capacitors) of the chip, is held below that reached during soldering in a soldering oven.

公开(公告)号：DE10125798B4

公开(公告)日：2006-01-19

申请号：DE10125798

申请日：2001-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MARX THILO ,  DIETRICH STEFAN ,  MAYER PETER ,  DOBLER MANFRED

IPC: G01B11/03 ,  G01B11/14 ,  G01R31/28 ,  G01R31/303 ,  G02B21/32 ,  H01L21/66

Abstract: The imaging system provides assistance during the positioning of a measuring tip as it is placed onto a contact region of a microchip, in order to measure an on-chip signal. The contact region is imaged in a magnified fashion. An insertion device is provided that is suitable for providing a display of the on-chip signal in the imaging plane.

公开(公告)号：DE10335618B4

公开(公告)日：2005-12-08

申请号：DE10335618

申请日：2003-08-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DOBLER MANFRED ,  BENZINGER HERBERT ,  KLIEWER JOERG ,  PROELL MANFRED

IPC: G11C8/08 ,  G11C11/406 ,  G11C11/408 ,  G11C11/407

Abstract: A semiconductor memory includes storage cells ( 2 ) that have storage capacitors and transistors with an electrode, which is electrically biasable with two different electrical potentials (V 1, V 2 ) in order to open and close the transistor. The electrode potential (V 2 ) intended for the off state of the transistor is a temperature-dependent potential, the value of which is controlled temperature-dependently by the semiconductor memory ( 1 ) so that the second electrical potential (V 2 ) becomes more different from the first electrical potential (V 1 ) as the temperature (T) increases.

公开(公告)号：DE10258199B4

公开(公告)日：2005-03-10

申请号：DE10258199

申请日：2002-12-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STOCKEN CHRISTIAN ,  PROELL MANFRED ,  DOBLER MANFRED ,  RESCH GERALD

IPC: G11C29/02 ,  G11C29/00

Abstract: A circuit arrangement can have a number of integrated circuit components, which are arranged on a carrier substrate. A reception circuit for receiving a control signal can be coupled to one of the connection pads on the input side and can be connected to each of the circuit components on the output side. A bridging circuit controlled by a test mode signal can electrically bridge the reception circuit. In a testing method, a plurality of connection pads can be connected to a first potential and at least one of the connection pads can be connected to a second potential. The bridging circuit can be activated and the current measured, by a test arrangement, at the at least one of the connection pads. Inspection for leakage currents in connections between input-side reception circuits and the circuit components can be measured.