公开(公告)号：DE10143650A1

公开(公告)日：2003-03-13

申请号：DE10143650

申请日：2001-09-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  STEINHOEGL WERNER ,  KERSCH ALFRED ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  LUETZEN JOERN ,  POPP MARTIN ,  SCHUMANN DIRK

IPC: H01L21/8242 ,  H01L27/108

Abstract: A semiconductor memory cell has trenches (25,50) in a substrate (15) having a capacitor (30) and long trenches having spacer wordlines with an active region between them having a vertical select transistor. Conductive bridges between wordlines in a trench are less than half as thick as the trench width. An Independent claim is also included for a process for making the above memory.

公开(公告)号：DE102005012112A1

公开(公告)日：2006-08-31

申请号：DE102005012112

申请日：2005-03-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN ,  WILLER JOSEF

IPC: H01L27/115 ,  G11C16/00 ,  H01L21/8247

Abstract: A thin SiGe layer is provided as an additional lower gate electrode layer and is arranged between a thin gate oxide and a gate electrode layer, preferably of polysilicon. The SiGe layer can be etched selectively to the gate electrode and the gate oxide and is laterally removed adjacent the source/drain regions in order to form recesses, which are subsequently filled with a material that is appropriate for charge-trapping. The device structure and production method are appropriate for an integration scheme comprising local interconnects of memory cells, a CMOS logic periphery and means to compensate differences of the layer levels in the array and the periphery.

公开(公告)号：DE102004037450A1

公开(公告)日：2006-03-16

申请号：DE102004037450

申请日：2004-08-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PINNOW CAY-UWE ,  GUTSCHE MARTIN

IPC: H01L29/68

Abstract: The invention relates to a method for operating a switching or amplifier device ( 11, 111 ), and to a switching or amplifier device ( 11, 111 ) comprising: an active material ( 13, 113 ) adapted to be placed in a more or less conductive state by means of appropriate switching processes; and at least three electrodes or contacts ( 12 a, 12 b, 12 c).

公开(公告)号：DE102004007410A1

公开(公告)日：2005-09-29

申请号：DE102004007410

申请日：2004-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L31/119

Abstract: The invention provides a method for fabricating a memory cell for storing electric charge, which has a substrate ( 101 ), which forms a first electrode, a trench-like recess ( 102 ) etched into the substrate ( 101 ), conductive material, which is provided as a projection in a central region of the trench-like recess ( 102 ) and spaced apart from the side walls ( 107 ) of the trench-like recess ( 102 ) and is in electrical contact with the substrate at the base ( 104 ) of the trench-like recess ( 102 ), a dielectric layer ( 108 ), which has been deposited on the side walls ( 107 ) of the trench-like recess ( 102 ), the base ( 104 ) of the trench-like recess ( 102 ) and the surfaces of the conductive material ( 105 ), and an electrode layer ( 110 ), which has been deposited on the dielectric layer ( 108 ) and forms a second electrode.

公开(公告)号：DE10345162A1

公开(公告)日：2005-05-19

申请号：DE10345162

申请日：2003-09-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/334 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108

公开(公告)号：DE69826934D1

公开(公告)日：2004-11-18

申请号：DE69826934

申请日：1998-06-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUTSCHE MARTIN ,  TOBBEN DIRK

IPC: H01L21/28 ,  H01L21/768

Abstract: A method for manufacturing a dual damascene structure includes the use of a sacrificial stud (12) and provides an improved defined edge on the interface between the conductive line openings (9) and the via openings (11).

公开(公告)号：DE10255841A1

公开(公告)日：2004-06-17

申请号：DE10255841

申请日：2002-11-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN

IPC: H01L21/02 ,  H01L21/3205 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: Process for structuring layers of ruthenium or ruthenium (IV) oxide comprises: (i) preparing a substrate; (ii) depositing a layer of ruthenium or ruthenium (IV) oxide on sections of the substrate; (iii) depositing a covering layer inert to oxygen on sections of the layer so that sections covered by the covering layer and free sections of the layer are obtained; (iv) tempering the substrate in an oxygen-containing atmosphere so that the exposed sections of the layer are converted into volatile ruthenium oxide and are removed from the substrate surface. An Independent claim is also included for a capacitor consisting of a first electrode plate (11) and a second electrode plate (14) with a dielectric (12) formed between the two plates.

公开(公告)号：DE10114956C2

公开(公告)日：2003-06-18

申请号：DE10114956

申请日：2001-03-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUTSCHE MARTIN ,  SEIDL HARALD

IPC: C23C14/08 ,  C23C16/40 ,  H01L21/28 ,  H01L21/316 ,  H01L21/8242 ,  H01L29/51

Abstract: Method of providing trench walls of a uniform orientation to support epitaxial growth in the trench. The trench is formed by a first etching process. A second etching process is used to change crystal orientation and thus create a widened trench with modified trench walls having a predetermined crystal orientation

公开(公告)号：DE10131709A1

公开(公告)日：2003-01-30

申请号：DE10131709

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  STEINHOEGL WERNER ,  KERSCH ALFRED ,  GUTSCHE MARTIN

IPC: H01L21/3213 ,  H01L21/8242

Abstract: Buried straps are produced on one side in deep trench structures. A PVD process is used to deposit masking material in the recess inclined at an angle. As a result, a masking wedge is produced on the buried strap, on one side in the base region of the recess. The masking wedge serves as a mask during a subsequent anisotropic etching step, which is carried out selectively with respect to the masking wedge, for removing the buried strap on one side.

公开(公告)号：DE10141084A1

公开(公告)日：2002-11-28

申请号：DE10141084

申请日：2001-08-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HECHT THOMAS ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  LEONHARDT MATTHIAS

IPC: C23C16/44 ,  C23C16/455 ,  C23C16/458 ,  C23C16/54

Abstract: Apparatus for depositing layers having atomic thickness on a substrate comprises a chamber with a first chamber region in which a first layer is deposited on a substrate, a second chamber region in which a second layer is deposited on the first layer and a transport system for transporting the substrate. The first and second chamber regions are separated by a chamber wall. Apparatus for depositing layers having atomic thickness on a substrate (5) comprises a chamber (10) with a first chamber region (15), into which a first process gas (20) is introduced to deposit a first layer (25) on the substrate, and a second chamber region (30), into which a second process gas (35) is introduced to deposit a second layer (40) on the first layer; and a transport system (45) to transport the substrates. A chamber wall (55) is arranged between the first chamber region and the second chamber region to separate the chamber regions. An Independent claim is also included for a process for depositing layers having atomic thickness on a substrate. Preferred Features: The chamber wall has a recess so that a substrate can pass through the chamber wall. A third chamber region (65) is arranged between the first chamber region and the second chamber region to separate the first and second chamber regions.